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the m pd17068 is a 4-bit single-chip microcontroller for digital tuning systems. it contains an image display controller (idc) that supports many types of display, and a pll synthesizer. the cpu of the m pd17068 is capable of 4-bit parallel addition, logical operations, bit tests, setting/resetting of a carry flag, and supports a powerful interrupt function and timer function. the image display controller for on-screen display is user-programmable, allowing a range of displays to be programmed. the peripheral hardware includes a full complement of i/o ports, controlled with powerful i/o instructions, as well as a serial interface, a 6-bit a/d converter, and an 8-bit d/a converter (pwm output). features ? program memory (rom) : 24k bytes (12032 16 bits) ? character rom (crom) : 4086 24 bits (255 characters) ? data memory (ram) : 1007 4 bits ? video ram (vram) : 672 4 bits (can be used for data memory) ? address stack : 12 levels ? interrupt stack : 2 levels ? instruction execution time : 2 m s (when an 8 mhz crystal is used) ? pll frequency synthesizer ? 8-bit serial interface (2 channels: one for two-wire or three-wire mode, compatible with i 2 c bus, and one for three-wire mode only) ? d/a converter: 8 bits 9 lines (pwm output) ? a/d converter: 6 bits 8 lines ? horizontal synchronizing signal counter ? commercial power supply frequency counter ? power-failure detection circuit and power-on reset circuit ? interrupt input for remote-controller signal (with noise canceler) ? user-programmable image display controller (idc) displayed characters : up to 192 per screen (more characters can be displayed when the use of the entire screen is specified with a program) display mode : 16 16 dots in 15 lines 24 columns 14 16 dots in 17 lines 24 columns character patterns : 255 character format : 16 16 dots or 14 16 dots colors : 15 character sizes : 16 sizes for height (can be specified per line) 24 sizes for width (can be specified per character) ? many i/o ports i/o : 19 ports input only : 4 ports output only : 21 ports ? operating supply voltage: 5 v 10 % ? low power dissipation by use of cmos technology the information in this document is subject to change without notice. data sheet mos integrated circuit m pd17068 4-bit single-chip microcontroller containing image display controller and pll frequency synthesizer for digital tuning systems 1994 document no. ic-3525 (o.d. no. ic-8999) date published november 1994 p printed in japan
2 m pd17068 ordering information part number package quality grade m pd17068gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd17068gf-e -3ba note 100-pin plastic qfp (14 20 mm) standard note product supporting an i 2 c bus interface. when using the i 2 c bus interface (including implementation with a program that does not use peripheral hardware), make this point clear to your nec sales representative when ordering mask options. remark is a rom code. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd17068 function overview item function program memory (rom) ? 24k bytes (12032 16 bits) table reference area: 12032 16 bits character rom (crom) ? 4086 24 bits (255 characters) data memory ram ? 1007 4 bits (including area also used for vram) data buffers: 4 4 bits, general-purpose registers: 16 4 bits video ram (vram) ? 672 4 bits (can be used for data memory (ram)) system registers ? 12 4 bits register files ? 12 4 bits general-purpose port registers ? 12 4 bits instruction execution time ? 2 m s (when 8 mhz crystal is used) stack levels ? 12 levels (stack manipulation possible) general-purpose ports ? i/o : 19 ports input only : 4 ports output only : 21 ports idc ? displayed characters : up to 192 per screen (more characters can be displayed (image display controller) when the use of the entire screen is specified with a program) ? display mode : 16 16 dots in 15 lines 24 columns 14 16 dots in 17 lines 24 columns ? character patterns : 255 (user-programmable) ? character format : 16 16 dots or 14 16 dots (2-dot interval can be specified between characters.) ? colors : 15 ? character sizes : 16 different heights (can be specified per line) 24 different widths (can be specified per character) pll frequency synthesizer ? frequency division method : pulse swallow ? reference frequency : 5, 6.25, 10, 12.5, and 25 khz ? contains a charge pump for an external low-pass filter ? phase comparator : unlock can be detected with a program. the delay for the unlock flip-flop is selectable. serial interface ? 2 channels serial interface 0 (two-wire or three-wire mode, compatible with i 2 c bus) serial interface 1 (three-wire mode only) d/a converter ? 8 bits 9 lines (pwm output with withstand voltage of 12.5 v max.) a/d converter ? 6 bits 8 lines (successive approximation system with software) interrupts ? 10 channels (maskable interrupts) external interrupts : 3 channels (int 0 , int nc , and v sync /h sync ) internal interrupts : 7 channels (timers 0 and 1, serial interfaces 0 and 1, basic timer 2, vram pointer, and timer 0 overflow)
4 m pd17068 item function timers timer 0 : 10 m s to 204.75 ms (interrupt) timer 1 : 1 m s to 256 ms (interrupt) basic timer 0 : 1, 5, and 100 ms (carry) basic timer 1 : 125 m s, 1 ms, 5 ms, 100 ms, and external (carry) basic timer 2 : 125 m s, 1 ms, 5 ms, 100 ms, and external (interrupt) watch timer : day, hour, minute, and second (count value) reset ? power-on reset ? reset with the ce pin (by switching the ce pin from low to high) ? power-failure detection function supply voltage 5 v 10% package 100-pin plastic qfp (14 20 mm) remark parentheses for timers indicate how to obtain the elapsed time for each timer. interrupt : receiving an interrupt carry : detecting the state of the carry flip-flop count value : reading the count value
5 m pd17068 vco psc eo osc in osc out h sync v sync red green blue blank i (pob 2 ) hscnt (p0b 3 ) p0a 0 -p0a 3 p0b 0 -p0b 3 p0c 0 -p0c 3 p0d 0 -p0d 3 p1a 0 -p1a 3 p1b 0 -p1b 3 p1c 0 -p1c 3 p1d 0 -p1d 3 p2a 0 p2b 0 -p2b 3 p2c 0 -p2c 3 p2d 0 -p2d 3 x in x out v dd ce rls stp /pib 2 gnd 0 , gnd 1 main osc reset cpu peripheral port pll osc circuit idc hsync counter ram 1007 4 bits vram (672 4 bits) system registers rf alu instruction decoder rom 12032 16 bits crom 4086 24 bits program counter stack 12 14 bits a/d converter d/a converter osc watch timer timer 0 timer 1 basic timer 0 basic timer 1 basic timer 2 serial interface 0 serial interface 1 interrupt adc 0 adc 1 (p0d 0 /xt out ) adc 2 (p0d 1 /xt in ) adc 3 (p0d 2 ) adc 4 (p0d 3 ) adc 5 (p1c 0 ) adc 7 (p1c 2 ) | pwm 0 (p2c 0 ) pwm 3 (p2c 3 ) pwm 4 (p2b 0 ) pwm 7 (p2b 3 ) pwm 8 (p2a 0 ) | | xt in (p0d 1 /adc 2 ) xt out (p0d 0 /adc 1 ) ckout (p1b 1 ) tmin (p1b 3 ) sda (p0a 0 ) scl (p0a 1 ) sck 0 (p0a 2 ) so 0 (p0a 3 ) si 0 (p0b 0 ) sck 1 (p2d 0 ) so 1 (p2d 1 ) si 1 (p2d 2 ) int nc int 0 4 4 4 4 4 4 4 4 4 4 3 block diagram
6 m pd17068 p0d 2 /adc 3 p0d 3 /adc 4 p1c 0 /adc 5 p1c 1 /adc 6 nc p1c 2 /adc 7 p1c 3 nc adc 0 nc p0c 0 nc p0c 1 nc p0c 2 nc p0c 3 nc p2c 1 /pwm 1 nc p2c 2 /pwm 2 nc p2c 3 /pwm 3 nc p2b 0 /pwm 4 p2b 1 /pwm 5 p2b 2 /pwm 6 p2b 3 /pwm 7 nc p2c 0 /pwm 0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p1d 2 p1d 1 p1d 0 int 0 nc p1b 3 /tmin p1b 2 /rls stp nc p1b 1 /ckout p1b 0 nc nc p1a 3 p1a 2 nc nc nc p1a 1 p1a 0 nc p2a 0 /pwm 8 nc nc p2d 2 /si 1 p2d 1 /so 1 p2d 0 /sck 1 nc gnd 0 0sc out 0sc in p1d 3 ce psc e0 vc0 gnd 2 gnd 1 nc nc nc nc nc nc v dd1 v dd0 x in x out int nc xt out /adc 1 /p0d 0 xt in /adc 2 /p0d 1 red green nc blue blank h sync nc v sync p0b 3 /hscnt nc nc p0b 2 /i p0b 1 nc p0b 0 /si 0 p0a 3 /so 0 p0a 2 /sck 0 nc p0a 1 /scl p0a 0 /sda pin configuration (top view) m pd17068gf- -3ba m pd17068gf-e -3ba
7 m pd17068 pins adc 0 C adc 7 : a/d converter input blank : blanking signal output blue : character signal output ce : chip enable ckout : watch timer adjustment output eo : error output gnd 0 , gnd 1 , gnd 2 : ground green : character signal output hscnt : input for horizontal synchronizing signal counter h sync : horizontal synchronizing signal input i : character signal output int 0 , int nc : input for external interrupt request signal osc in , osc out : lc oscillation i/o for idc p0a 0 - p0a 3 : port 0a p0b 0 - p0b 3 : port 0b p0c 0 - p0c 3 : port 0c p0d 0 - p0d 3 : port 0d p1a 0 - p1a 3 : port 1a p1b 0 - p1b 3 : port 1b p1c 0 - p1c 3 : port 1c p1d 0 - p1d 3 : port 1d p2a 0 : port 2a p2b 0 - p2b 3 : port 2b p2c 0 - p2c 3 : port 2c p2d 0 - p2d 2 : port 2d psc : pulse swallow control output pwm 0 - pwm 8 : pulse width modulation output red : character signal output rls stp : input for clock stop release signal scl : shift clock i/o sck 0 , sck 1 : shift clock i/o sda : serial data i/o si 0 , si 1 : serial data input so 0 , so 1 : serial data output tmin : event input for basic timer 1 or 2 vco : local oscillation input v dd0 , v dd1 : main power supply v sync : vertical synchronizing signal input x in , x out : main clock oscillation i/o xt in ,xt out : watch timer oscillation i/o
8 m pd17068 contents 1. pin functions ......................................................................................................................... 17 1.1 list of pin functions .............................................................................................................. 17 1.2 equivalent circuit of each pin .......................................................................................... 21 1.3 handling unused pins ............................................................................................................ 26 1.4 notes on use of the ce and int nc pins ............................................................................ 28 2. program memory (rom) .................................................................................................... 29 2.1 outline of program memory .............................................................................................. 29 2.2 program memory configuration ..................................................................................... 30 2.3 program counter .................................................................................................................... 31 2.3.1 program counter configuration .................................................................................. 31 2.3.2 segment register (sgr) ............................................................................................... 31 2.4 program flow ........................................................................................................................... 31 2.4.1 branch instructions ........................................................................................................ 31 2.4.2 subroutines ..................................................................................................................... 32 2.4.3 table reference .............................................................................................................. 32 2.4.4 system call ..................................................................................................................... 32 2.5 notes on use of program memory .................................................................................. 33 2.5.1 program counter and program memory size ........................................................... 33 2.5.2 last address of each segment .................................................................................... 33 3. address stack (ask) ............................................................................................................ 34 3.1 outline of address stack .................................................................................................... 34 3.2 address stack registers (asr) .......................................................................................... 34 3.3 stack pointer (sp) .................................................................................................................... 36 3.3.1 configuration and function of stack pointer ............................................................ 36 3.4 address stack operation ..................................................................................................... 37 3.4.1 subroutine call instruction (call addr or call @ar) and return instruction (ret or retsk) ..................................................................... 37 3.4.2 table reference instruction (movt dbf, @ar) .................................................... 37 3.4.3 interrupt reception and return instruction (reti) ............................................... 37 3.4.4 address stack manipulation instructions (push ar, pop ar) ...................... 37 3.4.5 system call instruction (syscal entry) and return instruction (ret or retsk) ....................................................................................................... 37 3.5 notes on use of address stack ........................................................................................ 37 3.5.1 nesting level .................................................................................................................. 37 4. data memory (ram) ............................................................................................................. 38 4.1 outline of data memory ...................................................................................................... 38 4.2 configuration and functions of data memory ....................................................... 39 4.2.1 system register (sysreg) ........................................................................................... 39 4.2.2 data buffer (dbf) ........................................................................................................... 39 4.2.3 vram (video ram) for the idc ................................................................................... 39 4.2.4 port register ................................................................................................................... 39 4.2.5 general-purpose data memory .................................................................................... 39 4.2.6 unmounted data memory ............................................................................................ 39
9 m pd17068 4.3 data memory addressing .................................................................................................... 42 4.4 notes on using data memory ............................................................................................ 42 4.4.1 power-on reset .............................................................................................................. 42 4.4.2 notes on unmounted data memory ........................................................................... 42 5. system register (sysreg) ................................................................................................. 43 5.1 outline of system register ................................................................................................ 43 5.2 format of system register ................................................................................................. 44 5.3 address register (ar) ............................................................................................................. 45 5.3.1 format of address register .......................................................................................... 45 5.3.2 address register functions .......................................................................................... 46 5.3.3 address register and data buffer ............................................................................... 46 5.3.4 notes on using address register ............................................................................... 46 5.4 window register (wr) ............................................................................................................ 47 5.4.1 format of window register ......................................................................................... 47 5.4.2 window register functions ......................................................................................... 47 5.5 bank register (bank) .............................................................................................................. 48 5.5.1 format of bank register ............................................................................................... 48 5.5.2 bank register functions ............................................................................................... 48 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) .............................................................................................................. 49 5.6.1 index register (ix) ......................................................................................................... 49 5.6.2 data memory row address pointer (mp) .................................................................. 50 5.7 general-purpose register pointer (rp) .......................................................................... 52 5.7.1 format of general-purpose register pointer ............................................................. 52 5.7.2 general-purpose register pointer functions ............................................................. 53 5.7.3 notes on using general-purpose register pointer ................................................... 53 5.8 program status word (psword) ...................................................................................... 54 5.8.1 format of program status word ................................................................................. 54 5.8.2 program status word functions ................................................................................. 55 5.8.3 notes on using program status word ....................................................................... 56 5.9 notes on using system register ...................................................................................... 56 6. general-purpose register (gr) ...................................................................................... 57 6.1 outline of general-purpose register ............................................................................ 57 6.2 general-purpose register body ....................................................................................... 57 6.3 general-purpose register address generation with instructions ............... 58 6.3.1 addition instructions (add r,m, addc r,m) subtraction instructions (sub r,m, subc r,m) logical operation instructions (and r,m, or r,m, xor r,m) direct transfer instructions (ld r,m, st m,r), and rotate instruction (rorc r) .......................................................................................... 58 6.3.2 indirect transfer instructions (mov @r,m, mov m,@r) .......................................... 58 6.4 notes on using general-purpose register ................................................................. 59 6.4.1 row address of general-purpose register ................................................................ 59 6.4.2 operation between general-purpose register and immediate data ..................... 59
10 m pd17068 7. arithmetic logic unit (alu) block ................................................................................ 60 7.1 overview ............................................................................................................................... ....... 60 7.2 configuration and functions of the components of the alu block ............ 61 7.2.1 alu ............................................................................................................................... .... 61 7.2.2 temporary storage registers a and b ....................................................................... 61 7.2.3 program status word .................................................................................................... 61 7.2.4 decimal conversion circuit .......................................................................................... 61 7.2.5 address controller ......................................................................................................... 61 7.3 alu operations ......................................................................................................................... 61 7.4 notes on using the alu ........................................................................................................ 65 7.4.1 notes on using the program status word for operations ..................................... 65 7.4.2 notes on performing decimal operations ................................................................. 65 8. register file (rf) ..................................................................................................................... 66 8.1 overview ............................................................................................................................... ....... 66 8.2 configuration and functions of the register file ................................................. 67 8.2.1 register file manipulation instructions (peek wr, rf and poke rf, wr) .............. 68 8.3 control registers ................................................................................................................... 68 8.4 notes on using the register file ..................................................................................... 79 9. data buffer (dbf) .................................................................................................................. 80 9.1 overview ............................................................................................................................... ....... 80 9.2 data buffer main body .......................................................................................................... 81 9.2.1 configuration of the data buffer main body ............................................................. 81 9.2.2 instruction to reference a table (movt dbf, @ar) ................................................ 82 9.2.3 instructions for controlling the peripheral hardware (put, get) ......................... 82 9.3 peripheral hardware and data buffer ......................................................................... 82 9.4 notes on using the data buffer ...................................................................................... 86 10. general-purpose ports .................................................................................................... 87 10.1 overview ............................................................................................................................... ....... 87 10.2 general-purpose i/o ports (p0a, p0b, p1b, p1c, p2d) ................................................... 89 10.2.1 configurations of the i/o ports ................................................................................... 89 10.2.2 using the i/o port .......................................................................................................... 92 10.2.3 control registers of the i/o ports ............................................................................... 93 10.2.4 using an i/o port as an input port .............................................................................. 98 10.2.5 using an i/o port as an output port ........................................................................... 98 10.2.6 notes on using the i/o port ......................................................................................... 98 10.2.7 statuses of the i/o ports upon reset ......................................................................... 99 10.3 general-purpose input port (p0d) .................................................................................... 99 10.3.1 configuration of the input port ................................................................................... 99 10.3.2 using the input port ...................................................................................................... 99 10.3.3 notes on using the input port ..................................................................................... 100 10.3.4 statuses of the input port upon reset ....................................................................... 100 10.4 general-purpose output ports (p0c, p1a, p1d, p2a, p2b, p2c) ................................. 100 10.4.1 configurations of the output ports ............................................................................. 100 10.4.2 using the output port ................................................................................................... 101 10.4.3 statuses of the output port upon reset .................................................................... 101
11 m pd17068 11. interrupt ............................................................................................................................... .. 102 11.1 outline of the interrupt block ........................................................................................ 102 11.2 interrupt control blocks ................................................................................................... 104 11.2.1 formats and functions of interrupt request flags (irq ) .................................. 104 11.2.2 interrupt enable flags (ip ) ...................................................................................... 110 11.2.3 vector address generator (vag) ................................................................................ 112 11.3 interrupt stack register ..................................................................................................... 113 11.3.1 format and functions of the interrupt stack register ............................................ 113 11.3.2 interrupt stack operation ............................................................................................. 113 11.4 stack pointer, address stack register, and program counter ....................... 114 11.5 interrupt enable flip-flop (inte) ....................................................................................... 114 11.6 accepting interrupts ............................................................................................................. 115 11.6.1 operation for accepting interrupts and priorities .................................................... 115 11.6.2 timing charts for accepting interrupts ...................................................................... 116 11.7 operation after an interrupt is accepted .................................................................. 119 11.8 return from the interrupt handling routine ........................................................... 119 11.9 external interrupts (int 0 pin, int nc pin, v sync pin, h sync pin) ................................... 120 11.9.1 outline of external interrupts ...................................................................................... 120 11.9.2 edge detection blocks ................................................................................................... 121 11.9.3 interrupt control block ................................................................................................. 122 11.9.4 input pin for remote control (int nc ) .......................................................................... 123 11.10 internal interrupts ............................................................................................................... 123 11.10.1 timer 0 interrupt ............................................................................................................ 124 11.10.2 timer 1 interrupt ............................................................................................................ 124 11.10.3 basic timer 2 interrupt ................................................................................................. 124 11.10.4 vram pointer interrupt ................................................................................................ 124 11.10.5 serial interface 0 interrupt ........................................................................................... 124 11.10.6 serial interface 1 interrupt ........................................................................................... 124 11.10.7 interrupts by interrupt group 0 and interrupt group selection register ............. 125 12. timers ............................................................................................................................... ......... 126 12.1 overview ............................................................................................................................... ....... 126 12.2 basic timer 0 ............................................................................................................................... 128 12.2.1 overview of basic timer 0 ............................................................................................ 128 12.2.2 clock selection block .................................................................................................... 128 12.2.3 flip-flop and btm0cy flag .......................................................................................... 129 12.2.4 example of using basic timer 0 .................................................................................. 130 12.2.5 time interval error in basic timer 0 ........................................................................... 131 12.2.6 cautions for using basic timer 0 ................................................................................ 134 12.3 basic timer 1 ............................................................................................................................... 140 12.3.1 overview of basic timer 1 ............................................................................................ 140 12.3.2 clock selection block .................................................................................................... 141 12.3.3 flip-flop and btm1cy flag .......................................................................................... 142 12.3.4 time interval error in basic timer 1 ........................................................................... 142 12.4 basic timer 2 ............................................................................................................................... 143 12.4.1 overview of basic timer 2 ............................................................................................ 143 12.4.2 clock selection block .................................................................................................... 144 12.4.3 example of using basic timer 2 .................................................................................. 145
12 m pd17068 12.4.4 time interval error in basic timer 2 ........................................................................... 145 12.4.5 cautions for using basic timer 2 ................................................................................ 148 12.5 timer 0 ............................................................................................................................... ............ 150 12.5.1 overview of timer 0 ...................................................................................................... 150 12.5.2 clock selection block .................................................................................................... 151 12.5.3 count block ..................................................................................................................... 152 12.5.4 example of using timer 0 ............................................................................................ 155 12.5.5 time interval error in timer 0 ...................................................................................... 156 12.5.6 cautions for using timer 0 .......................................................................................... 156 12.6 timer 1 ............................................................................................................................... ............ 157 12.6.1 overview of timer 1 ...................................................................................................... 157 12.6.2 clock selection block .................................................................................................... 158 12.6.3 count block ..................................................................................................................... 159 12.6.4 time interval error in timer 1 ...................................................................................... 161 12.6.5 cautions for using timer 1 .......................................................................................... 161 12.7 clock timer ............................................................................................................................... .. 162 12.7.1 overview of the clock timer ........................................................................................ 162 12.7.2 clock frequency divider block ..................................................................................... 163 12.7.3 count block ..................................................................................................................... 165 12.7.4 reset control block ....................................................................................................... 169 12.7.5 32 khz oscillator and oscillation frequency adjustment ........................................ 170 12.7.6 cautions for using the clock timer ............................................................................ 170 13. a/d converter ....................................................................................................................... 171 13.1 outline of a/d converter .................................................................................................... 171 13.2 input switching block ........................................................................................................... 172 13.3 compare voltage generation block and compare block .................................... 174 13.4 compare timing chart ........................................................................................................... 178 13.5 a/d converter performance .............................................................................................. 178 13.6 using a/d converter .............................................................................................................. 179 13.6.1 comparison with one reference voltage .................................................................. 179 13.6.2 successive approximation based on the binary search method .......................... 180 13.7 notes on using a/d converter .......................................................................................... 184 13.8 states upon reset ................................................................................................................... 184 13.8.1 power-on reset .............................................................................................................. 184 13.8.2 clock stop ....................................................................................................................... 184 13.8.3 ce reset .......................................................................................................................... 184 14. d/a converter (pwm method) ......................................................................................... 185 14.1 outline of d/a converter .................................................................................................... 185 14.2 output switching block ....................................................................................................... 186 14.3 duty cycle setting block ..................................................................................................... 188 14.4 clock generation block ....................................................................................................... 190 14.5 output waveforms of d/a converter ........................................................................... 190 14.6 notes on using d/a converter .......................................................................................... 191 14.7 states upon reset ................................................................................................................... 191 14.7.1 power-on reset .............................................................................................................. 191 14.7.2 clock stop ....................................................................................................................... 191
13 m pd17068 14.7.3 ce reset .......................................................................................................................... 191 14.7.4 halt state ........................................................................................................................ 191 15. serial interface .................................................................................................................... 192 15.1 general ............................................................................................................................... .......... 192 15.2 serial interface 0 ..................................................................................................................... 193 15.2.1 general ............................................................................................................................ 193 15.2.2 clock i/o control block and data i/o control block ................................................ 194 15.2.3 clock control block ....................................................................................................... 197 15.2.4 clock counter and start/stop detection block ......................................................... 197 15.2.5 presettable shift register 0 .......................................................................................... 199 15.2.6 wait control block and acknowledge control block ............................................... 200 15.2.7 interrupt control block ................................................................................................. 202 15.2.8 i 2 c bus mode ................................................................................................................... 203 15.2.9 serial i/o mode .............................................................................................................. 210 15.2.10 data write and read cautions ..................................................................................... 214 15.2.11 serial interface 0 operation .......................................................................................... 215 15.2.12 state when serial interface 0 is reset ....................................................................... 218 15.3 serial interface 1 ..................................................................................................................... 219 15.3.1 general ............................................................................................................................ 219 15.3.2 clock i/o control block and data i/o control block ................................................ 219 15.3.3 clock counter ................................................................................................................. 220 15.3.4 presettable shift register 1 .......................................................................................... 222 15.3.5 wait control block ......................................................................................................... 222 15.3.6 serial interface 1 operation .......................................................................................... 223 15.3.7 data write and data read cautions ........................................................................... 226 15.3.8 serial interface 1 operation .......................................................................................... 227 15.3.9 state when serial interface 1 is reset ....................................................................... 228 16. image display controller (idc) ..................................................................................... 229 16.1 general ............................................................................................................................... .......... 229 16.1.1 configuration .................................................................................................................. 229 16.1.2 idc functions .................................................................................................................. 230 16.2 idc display control block ................................................................................................... 231 16.2.1 idc display control block control registers ............................................................. 231 16.2.2 display format ............................................................................................................... 233 16.2.3 space between characters ........................................................................................... 233 16.2.4 screen background color ............................................................................................. 235 16.3 idc start position control block .................................................................................... 235 16.3.1 configuration of idc start position setting register ............................................... 235 16.3.2 horizontal start position setting ................................................................................ 236 16.3.3 vertical start position setting ..................................................................................... 237 16.4 crom (character rom) ........................................................................................................... 239 16.4.1 character pattern data configuration ........................................................................ 240 16.4.2 definition of character pattern data with assembler .............................................. 242 16.5 vram (video ram) ...................................................................................................................... 243 16.5.1 general ............................................................................................................................ 243 16.5.2 configuration of vram data ........................................................................................ 244
14 m pd17068 16.5.3 character pattern selection data ................................................................................ 245 16.5.4 carriage return data (c/r) ........................................................................................... 248 16.5.5 control data .................................................................................................................... 248 16.5.6 vram data setting example ....................................................................................... 253 16.5.7 vram data setting cautions ....................................................................................... 253 16.6 vram pointer .............................................................................................................................. 2 55 16.6.1 configuration of vram pointer ................................................................................... 255 16.6.2 vram pointer buffer (idcvp) ....................................................................................... 256 16.6.3 vram pointer register (idcvpr) ................................................................................ 257 16.7 idc output pins (blank, red, green, blue, i pins) ........................................................ 258 16.7.1 functions of idc output pins ....................................................................................... 258 16.7.2 idc output waveforms ................................................................................................. 258 16.8 sample program ....................................................................................................................... 259 16.8.1 displaying data exceeding vram capacity (extended display mode) ................. 259 17. horizontal synchronizing signal counter ............................................................ 262 17.1 general ............................................................................................................................... .......... 262 17.2 gate input amplifier ............................................................................................................... 262 17.3 gate control ............................................................................................................................. 26 3 17.3.1 h sync counter gate mode selection flag (hscgt ) ................................................ 264 17.3.2 h sync counter gate open status flag (hscgostt) ................................................ 264 17.4 h sync counter data register (hsc) .................................................................................... 265 17.5 sample program ....................................................................................................................... 265 17.6 state at reset ........................................................................................................................... 265 18. pll frequency synthesizer ............................................................................................. 266 18.1 general ............................................................................................................................... .......... 266 18.2 programmable divider .......................................................................................................... 267 18.2.1 configuration .................................................................................................................. 267 18.2.2 programmable divider and pll data register .......................................................... 268 18.3 reference frequency generator ..................................................................................... 269 18.4 phase comparator ( f -det), charge pump and unlock detection block ......... 271 18.4.1 configuration of phase comparator, charge pump and unlock detection block ................................................................................................. 271 18.4.2 phase comparator functions ....................................................................................... 271 18.4.3 charge pump .................................................................................................................. 272 18.4.4 configuration and functions of unlock detection block ......................................... 273 18.4.5 organization and functions of pll unlock flip-flop judge register .................... 273 18.4.6 organization and functions of pll unlock flip-flop sensibility selection register .......................................................................................................... 274 18.5 pll disabled state ................................................................................................................... 274 18.6 pll frequency synthesizer use ......................................................................................... 275 18.7 sample program ....................................................................................................................... 276 18.8 state at reset ........................................................................................................................... 277 18.8.1 at power-on reset ........................................................................................................ 277 18.8.2 at clock-stop .................................................................................................................. 277 18.8.3 at ce reset ..................................................................................................................... 277 18.8.4 during the halt state .................................................................................................... 277
15 m pd17068 19. standby ............................................................................................................................... ..... 278 19.1 standby functions .................................................................................................................. 278 19.2 halt function ............................................................................................................................ 280 19.2.1 general ............................................................................................................................ 280 19.2.2 halt state ........................................................................................................................ 280 19.2.3 halt release conditions ................................................................................................ 280 19.2.4 halt release by key input ............................................................................................. 281 19.2.5 halt release by basic timer 0 ...................................................................................... 283 19.2.6 halt release by interrupt .............................................................................................. 283 19.2.7 when multiple release conditions set simultaneously .......................................... 286 19.3 clock-stop function .............................................................................................................. 287 19.3.1 clock-stop state ............................................................................................................ 287 19.3.2 clock-stop state release .............................................................................................. 287 19.3.3 clock-stop release by ce reset .................................................................................. 287 19.3.4 clock-stop release by power-on reset ..................................................................... 288 19.3.5 clock-stop release by r1b 2 /rls stp pin ..................................................................... 289 19.3.6 cautions when using clock-stop instruction ........................................................... 291 19.4 device operation at halt and clock-stop .................................................................... 292 19.5 pin processing cautions in halt state and clock-stop state ........................... 293 19.6 device operation control by ce pin ................................................................................ 296 19.6.1 image display controller (idc) operation control .................................................... 296 19.6.2 pll frequency synthesizer operation control ......................................................... 296 19.6.3 clock-stop instruction disable/enable control ......................................................... 296 19.6.4 device reset ................................................................................................................... 296 19.6.5 signal input to ce pin ................................................................................................... 297 19.6.6 organization and functions of ce pin level judge register .................................. 297 19.6.7 organization and functions of ce pin edge detection register ............................ 298 20. reset ............................................................................................................................... ............. 299 20.1 reset block configuration ................................................................................................. 299 20.2 reset function .......................................................................................................................... 300 20.3 ce reset ............................................................................................................................... .......... 301 20.3.1 ce reset when clock-stop (stop s instruction) not used .................................... 301 20.3.2 ce reset when clock-stop (stop s instruction) used ............................................ 302 20.3.3 cautions at ce reset ..................................................................................................... 303 20.4 power-on reset ......................................................................................................................... 304 20.4.1 power-on reset at normal operation ........................................................................ 305 20.4.2 power-on reset in clock-stop state .......................................................................... 305 20.4.3 power-on reset when v dd rises from 0 v ............................................................... 305 20.5 relationship between ce reset and power-on reset .............................................. 307 20.5.1 when v dd pin and ce pin rise simultaneously ......................................................... 307 20.5.2 when ce pin raised in forced halt state caused by power-on reset. ................ 307 20.5.3 when ce pin raised after power-on reset ............................................................... 307 20.5.4 cautions when v dd raised ........................................................................................... 309 20.6 power failure detection ...................................................................................................... 311 20.6.1 power failure detection circuit ................................................................................... 311 20.6.2 cautions at power failure detection with btm0cy flag ........................................ 314 20.6.3 power failure detection by ram judgment ............................................................. 316 20.6.4 cautions at power failure detection by ram judgment ........................................ 318
16 m pd17068 21. instruction set .................................................................................................................... 319 21.1 list of instruction set .......................................................................................................... 319 21.2 instructions .............................................................................................................................. 3 20 21.3 assembler (as17k) built-in macro instructions ....................................................... 323 22. reserved symbols ............................................................................................................... 324 22.1 data buffer (dbf) ...................................................................................................................... 324 22.2 system register (sysreg) ..................................................................................................... 324 22.3 vram bank register ................................................................................................................ 324 22.4 port register ............................................................................................................................. 32 5 22.5 register files ............................................................................................................................. 32 7 22.6 peripheral hardware register .......................................................................................... 331 22.7 others ............................................................................................................................... ............ 331 23. electrical characteristics ............................................................................................. 332 24. package drawings ............................................................................................................... 335 25. recommended soldering conditions ....................................................................... 336 appendix a. notes on connecting a crystal ................................................................ 337 appendix b. development tools .......................................................................................... 338
17 m pd17068 1. pin functions 1.1 list of pin functions (1) port pins pin function i/o output type at reset also used as: p0a 0 i/o n-ch open drain input sda p0a 1 scl p0a 2 cmos push-pull sck 0 p0a 3 so 0 p0b 0 i/o cmos push-pull input si 0 p0b 1 C p0b 2 i p0b 3 hscnt p0c 0 output cmos push-pull outputs C | undefined data. p0c 3 p0d 0 4-bit input port input C input with a pull- adc 1 /xt out p0d 1 adc 2 /xt in p0d 2 adc 3 p0d 3 adc 4 p1a 0 4-bit output port output outputs C | undefined data. p1a 3 p1b 0 i/o cmos push-pull input C p1b 1 ckout p1b 2 rls stp p1b 3 tmin p1c 0 i/o cmos push-pull input adc 5 | | p1c 2 adc 7 p1c 3 C p1d 0 4-bit output port output cmos push-pull outputs C | undefined data. p1d 3 p2a 0 1-bit output port output outputs pwm 3 undefined data. p2b 0 4-bit output port output n-ch open drain outputs pwm 4 | with intermediate undefined data. | p2b 3 withstand voltage pwm 7 p2c 0 4-bit output port output n-ch open drain outputs pwm 0 | with intermediate undefined data. | p2c 3 withstand voltage pwm 3 p2d 0 i/o cmos push-pull input sck 1 p2d 1 so 1 p2d 2 si 1 4-bit i/o port. input or output mode can be specified in bit units. the pins are automatically set to input mode when the power (v dd ) is turned on, the clock is stopped, or the device is reset with the ce pin. 4-bit i/o port. input or output mode can be specified in bit units. the pins are automatically set to input mode when the power (v dd ) is turned on, the clock is stopped, or the device is reset with the ce pin. 4-bit output port. undefined data is output when the power (v dd ) is turned on. 4-bit i/o port. input or output mode can be specified in bit units. 4-bit i/o port. input or output mode can be specified in 4-bit units. down registor n-ch open drain with intermediate with- stand voltage and high current n-ch open drain with intermediate with- stand voltage 3-bit i/o port. input or output mode can be specified in bit units. the pins are automatically set to input mode when the power (vdd) is turned on, the clock is stopped, or the device is reset with the ce pin.
18 m pd17068 (2) non-port pins pin function i/o output type at reset also used as: int 0 input pin for an external interrupt input C input C request signal. an interrupt request is triggered by the rising or falling edge of the signal input to this pin. int nc input pin for an interrupt request input C input C signal with a noise canceler. when inputting a signal subject to much noise, such as a remote- controller signal, use this pin to facilitate programming. whether the rising or falling edge of the input signal is used to trigger an interrupt request can be specified with a program. tmin event input pin for basic timer 1 or 2 input C input pib 3 xt in C C C p0d 1 /adc 2 xt out p0d 0 /adc 1 ckout output pin for adjusting the watch timer output cmos push-pull input p1b 1 sck 0 shift clock i/o pins i/o cmos push-pull input p0a 2 sck 1 p2d 0 si 0 serial data input pins input C input p0b 0 si 1 p2d 2 so 0 serial data output pins output cmos push-pull input p0a 3 so 1 p2d 1 scl shift clock i/o pin i/o n-ch open drain input p0a 1 sda serial data i/o pin i/o n-ch open drain input p0a 0 adc 0 input C input C adc 1 p0d 0 /xt out adc 2 p0d 1 /xt in adc 3 p0d 2 adc 4 p0d 3 adc 5 analog input pins for the a/d input C input p1c 0 | converter with 6-bit resolution | adc 7 p1c 2 pwm 0 output pins for the d/a converter output n-ch open drain low-level output p2c 0 | with 8-bit resolution with intermediate or high imped- | pwm 3 withstand voltage ance p2c 3 pwm 4 p2b 0 | | pwm 7 p2b 3 pwm 8 p2a 0 pins for connecting the crystal (32.768 khz) for the watch timer analog input pins for the a/d converter with 6-bit resolution
19 m pd17068 pin function i/o output type at reset also used as: eo output pin for the charge pump of the output cmos tristate high impedance C pll frequency synthesizer. when the divided local oscillation (vco) frequency is higher than the reference frequency, the output of this pin goes to high level. when the divided frequency is lower than the reference frequency, the output of this pin goes to low level. when the frequencies are the same, this pin enters floating status. psc output pin for pulse swallow control. output cmos push-pull output C this pin is used to output a signal to change the frequency division ratio to the m pb595 dedicated prescaler. vco local oscillation input pin. input C internally pulled- C the local oscillation (vco) output from down the tuner is frequency-divided by the m pb595 dedicated prescaler and input to this pin (the m pb595 is a two- modulus prescaler for up to 1 ghz). hscnt input pin for horizontal synchronizing input C input p0b 3 signal counter. blank output pin for the blanking signal for output cmos push-pull low-level output C cutting the video signal. the signal is high active. red output pin for the r signal for output cmos push-pull low-level output C character data received from the idc. the signal is high active. green output pin for the g signal for output cmos push-pull low-level output C character data from the idc. the signal is high active. blue output pin for the b signal for output cmos push-pull low-level output C character data from the idc. the signal is high active. i output pin for the i signal for character output cmos push-pull input p0b 2 data from the idc. h sync input pin for the horizontal synchro- input C input C nizing signal for the idc. used to input the active-low horizontal synchronizing signal. v sync input pin for the vertical synchronizing input C input C signal for the idc. used to input the active-low vertical synchronizing signal. osc in C C C C osc out pins for connecting the lc oscillation circuit for the idc. used to connect a 10 mhz lc oscillation circuit.
20 m pd17068 pin function i/o output type at reset also used as: ce input pin for the device operation input C input _ selection signal and reset signal. (1) device operation selection signal when the device operation selection signal at the ce pin is high, the pll frequency synthe- sizer and idc are enabled. when the signal is low, the pll frequency synthesizer and idc are disabled. (2) reset signal when the reset signal at the ce pin is changed from low to high, the device is reset in synchroniza- tion with the internal carry flip-flop for basic interval timer 0. rls stp input pin for the clock stop release input C input p1b 2 signal x in CC C C x out v dd0 main power supply pins. supply 5 v 10% when operating the C C C C entire device. supply 4.0 to 5.5 v when the idc is not being used. the minimum supply voltage is 2.5 v in the clock-stop state. a power-on reset circuit is provided. when the supply voltage increases from 0 to 4.0 v, the system is reset and the program restarts at address 0. the voltage must increase from 0 to 4.0 v within 500 ms to enable correct operation of the power-on reset circuit. gnd 0 ground pins C C C C | gnd 2 nc no connection C C C C pins for connecting a crystal (8 khz) for the main clock v dd1
21 m pd17068 1.2 equivalent circuit of each pin (1) p0a (p0a 3 /so 0 , p0a 2 /sck 0 ) p0b (p0b 2 /i, p0b 1 , p0b 0 /si 0 ) p1b (p1b 2 /rls stp , p1b 1 /ckout, p1b 0 ) p1c (p1c 3 , p1c 2 /adc 7 , p1c 1 /adc 6 , p1c 0 /adc 5 ) v dd v dd a/d converter (only for p1c/adc) res signal (except for p1c) a/d converter channel select signal (only for p1c) (2) p2d (p2d 2 /si 1 , p2d 1 /so 1 , p2d 0 /sck 1 ) : (i/o) v dd v dd res signal (i/o)
22 m pd17068 v dd res signal (3) p0a (p0a 1 /scl, p0a 0 /sda) : (i/o) (4) p0c (p0c 3 , p0c 2 , p0c 1 , p0c 0 ) p1d (p1d 3 , p1d 2 , p1d 1 , p1d 0 ) red, green, blue, blank psc (output) v dd (5) p1a (p1a 3 , p1a 2 , p1a 1 , p1a 0 ) p2a (p2a 0 /pwm 8 ) p2b (p2b 3 /pwm 7 , p2b 2 /pwm 6 , p2b 1 /pwm 5 , p2b 0 /pwm 4 ) p2c (p2c 3 /pwm 3 , p2c 2 /pwm 2 , p2c 1 /pwm 1 , p2c 0 /pwm 0 ) (output) (6) p0d (p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in , p0d 0 /adc 1 /xt out ) : (input) v dd high on-state resistance
23 m pd17068 (7) adc 0 : (input) v dd (8) p0b 3 /hscnt : (i/o) v dd v dd read instruction port horizontal synchronizing signal counter
24 m pd17068 (9) p1b 3 /tmin : (i/o) v dd v dd v dd v dd read instruction port timer counter (10) h sync , v sync , ce, int 0 , int nc : (schmitt-triggered input) v dd
25 m pd17068 (11) x in , osc in : (input) x out , osc out : v dd v dd x in , osc in x out , osc out high on-state resistance (12) eo : (output) v dd (13) vco : (input) v dd v dd (input)
26 m pd17068 1.3 handling unused pins connect unused pins as follows: table 1-1 handling unused pins (1/2) pin i/o recommended connection when not used p0a 0 /sda i/o input: connect to v dd or v ss . p0a 1 /scl output: output a low and leave open. p0a 2 /sck 0 i/o input: connect to v dd or v ss . p0a 3 /so 0 output: leave open. p0b 0 /si 0 p0b 1 p0b 2 /i p0b 3 /hscnt p0c 0 output leave open. | p0c 3 p0d 0 /adc 1 /xt out input with a pull-down leave open or connect to v ss . p0d 1 /adc 2 /xt in resistor. p0d 2 /adc 3 p0d 3 /adc 4 p1a 0 n-ch open-drain output output a low and leave open. | p1a 3 p1b 0 i/o input: connect to v dd or v ss . p1b 1 /ckout output: leave open. p1b 2 /rls stp p1b 3 /tmin p1c 0 /adc 5 | p1c 2 /adc 7 p1c 3 p1d 0 output leave open. | p1d 3 p2a 0 /pwm 8 n-ch open-drain output output a low and leave open. p2b 0 /pwm 4 | p2b 3 /pwm 7 p2c 0 /pwm 0 | p2c 3 /pwm 3 p2d 0 /sck 1 i/o input: connect to v dd or v ss . p2d 1 /so 1 output: leave open. p2d 2 /si 1
27 m pd17068 table 1-1 handling unused pins (2/2) pin i/o recommended connection when not used eo output leave open. psc vco input with a pull-down leave open or connect to v ss . resistor blank output leave open. red green blue h sync input connect to v dd or v ss . v sync osc in input with a pull-down leave open or connect to v ss . resistor osc out output leave open. adc 0 input connect to v dd or v ss . int 0 int nc
28 m pd17068 1.4 notes on use of the ce and int nc pins the ce and int nc pins support a test mode for selecting the function for testing the internal operation of the m pd17068 (ic test), in addition to the functions described in section 1.1 . applying a voltage exceeding v dd to the ce or int nc pin causes the m pd17068 to enter test mode. if noise exceeding v dd is encountered during normal operation, the device will be switched to test mode. for example, if the wiring from the ce or int nc pin is too long, noise may be induced in the wiring, thus resulting in this mode switching. when installing wiring, route the wiring such that noise is suppressed as much as possible. if, however, noise arises, use an external part to suppress it as shown below. v dd v dd ce, int nc ce, int nc v dd v dd diode with low v f l l connect a capacitor between the pin and v dd . l l connect a diode with low v f between the pin and v dd .
29 m pd17068 2. program memory (rom) 2.1 outline of program memory fig. 2-1 outlines program memory. as shown, program memory is addressed with a program counter. program memory has the following functions: (1) storing programs (2) storing constant data fig. 2-1 outline of program memory program counter addressing program memory instruction constant data
30 m pd17068 2.2 program memory configuration fig. 2-2 shows the configuration of program memory. as shown, program memory consists of 24k bytes (12032 16 bits). program memory therefore has addresses 0000h to 2fffh. program memory addresses 3000h to 4fdfh are assigned to the crom (character rom) area. this area cannot be used as an ordinary program area. all m pd17068 instructions are 16-bit one-word instructions. each instruction can be stored at a single address of program memory. constant data stored in program memory is read into the data buffer by executing a table reference instruction. fig. 2-2 program memory configuration 16 bits page 0 page 1 page 2 page 3 0000h 07ffh 0800h 1000h 17ffh 1800h 1effh 1f00h 1fffh 2000h 27ffh 2800h 2fffh 3000h 3fffh 4000h 4fdfh segment 0 segment 1 (system segment) segment 2 2000h 20ffh 2100h 21ffh 2200h 22ffh 2300h 25ffh 2600h 26ffh 2700h block 0 block 1 block 2 block 6 block 7 undefined page 0 page 1 crom area note (cannot be used as program area) 27ffh note addresses in the crom area are specified with vram. addresses that can be specified with vram are 3000h to 3fefh. an address in the crom area, however, has 32 bits because crom data is represented in 24-bit units. therefore, the crom addresses which are actually used (actual addresses) are 3000h to 4fdfh (see chapter 16 ).
31 m pd17068 2.3 program counter 2.3.1 program counter configuration fig. 2-3 shows the configuration of the program counter. as shown, the program counter consists of a 13-bit binary counter and 1-bit segment register (sgr). bits 11 and 12 indicate a page. the program counter is used to specify an address in program memory. fig. 2-3 program counter configuration sgr pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc page 2.3.2 segment register (sgr) the segment register specifies a segment of program memory. table 2-1 lists the correspondence between segment register values and program memory segments. the segment register is set when a syscal entry instruction is executed. table 2-1 correspondence between segment register values and program memory segments segment register value program memory segment 0 segment 0 1 segment 1 2.4 program flow the execution flow of a program is controlled with the program counter, which specifies an address in program memory. this section describes the operation of several types of instructions. fig. 2-4 shows the value set in the program counter when each instruction is executed. table 2-2 lists the vector addresses when interrupts are received. 2.4.1 branch instructions (1) direct branch (br addr) a direct branch instruction can branch only within the same segment of program memory. (2) indirect branch (br @ar) an indirect branch instruction can branch to all addresses of program memory, 0000h to 2fffh. see also section 5.3 .
32 m pd17068 2.4.2 subroutines (1) direct subroutine call (call addr) a direct subroutine call instruction can call a subroutine starting at an address in page 0 in program memory. (2) indirect subroutine call (call @ar) an indirect subroutine call instruction can call a subroutine starting at any address in program memory, 0000h to 2fffh. see also section 5.3 . 2.4.3 table reference a table reference instruction (movt dbf, @ar) can reference all addresses in program memory, 0000h to 2fffh. see also sections 5.3 and 9.2.2 . 2.4.4 system call a system call instruction (syscal entry) can call a subroutine starting at any of the first 16 addresses of a block (0 to 7) in page 0 of segment 1. fig. 2-4 program counter value for each instruction program counter page 0 page 1 page 2 page 3 00 01 10 11 sgr b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 value of program counter (pc) 00 00 1 entry h entry l 0000 0 00000000000000 br addr call addr syscal entry br call movt dbf, @ar @ar @ar ret retsk reti instruction instruction operand (addr) instruction operand (addr) when an interrupt is received at power-on reset or ce reset hold hold contents of address register return address: contents of address stack register (asr) specified with stack pointer (sp) vector address for the interrupt remark entry h : three high-order bits of entry entry l : four low-order bits of entry
33 m pd17068 table 2-2 interrupt vector addresses priority internal/external interrupt source vector address 1 external int nc pin 000ah 2 external int 0 pin 0009h 3 internal timer 0 0008h 4 internal timer 1 0007h 5 internal basic timer 2 0006h 6 internal vram pointer 0005h 7 external interrupt group 1 note 1 0004h 8 internal serial interface 0 0003h 9 internal serial interface 1 0002h 10 internal interrupt group 0 note 2 0001h notes 1. interrupt group 1 : v sync or h sync pin 2. interrupt group 0 : timer 0 overflow 2.5 notes on use of program memory 2.5.1 program counter and program memory size the program counter can specify addresses 0000h to 3fffh, while the valid program memory addresses are 0000h to 1effh and 2000h to 2fffh. therefore, do not use an instruction specifying addresses 1f00h to 1fffh or 3000h to 3fffh. program memory addresses 1f00h to 1fffh contain undefined values. addresses 3000h to 3fffh constitute the crom area, which cannot be specified with the program counter. 2.5.2 last address of each segment the segment register is not connected the binary counter. the last address of segment 0, 1fffh, is followed by address 0000h of the same segment. use instructions such as indirect branch, indirect subroutine call, and system call to specify another segment.
34 m pd17068 3. address stack (ask) 3.1 outline of address stack fig. 3-1 outlines the address stack. the address stack consists of the stack pointer and address stack registers. the stack pointer is used to specify one of the address stack registers. the address stack is used to store the return address when a subroutine call instruction is executed or an interrupt is received. the address stack is also used when a table reference instruction is executed. fig. 3-1 outline of address stack stack pointer addressing address stack registers return address 3.2 address stack registers (asr) fig. 3-2 shows the configuration of the address stack registers. there are 13 address stack registers, asr0 to asr12, each consisting of 14 bits. asr12, however, cannot be used, the twelve 14-bit registers (asr0 to asr11) actually being used. the most significant bit of each address stack register is the segment register stack (sgrsk), the other 13 bits being used as the program counter stack (pcsk). the address stack is used to store the return address when a subroutine call or table reference instruction is executed or an interrupt is received.
35 m pd17068 fig. 3-2 configuration of address stack registers stack pointer (sp) bits b 3 b 2 b 1 b 0 sp3 sp2 sp1 sp0 address stack registers (asr) address bits b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 asr0 asr1 asr2 asr3 asr4 asr5 asr6 asr7 asr8 asr9 asr10 asr11 asr12 (undefined) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch cannot be used.
36 m pd17068 3.3 stack pointer (sp) 3.3.1 configuration and function of stack pointer fig. 3-3 shows the configuration and function of the stack pointer. the stack pointer is a 4-bit binary counter, used for specifying an address stack register. the value of the stack pointer can be directly read or written with a register manipulation instruction. fig. 3-3 configuration and function of stack pointer 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 asr0 asr1 asr2 asr3 asr4 asr5 asr6 asr7 asr8 asr9 asr10 asr11 asr12 specifies an address stack register (asr). b 3 b 2 b 1 b 0 address read/write 01h r/w flag symbol stack pointer (sp) upon reset power-on clock stop ce 1100 1100 1100 ( s p 3 ( s p 2 ( s p 1 ( s p 0 name
37 m pd17068 3.4 address stack operation 3.4.1 subroutine call instruction (call addr or call @ar) and return instruction (ret or retsk) when a subroutine call instruction is executed, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. when a return instruction is executed, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.2 table reference instruction (movt dbf, @ar) when a table reference instruction is executed, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. next, the contents of the program memory address specified with the address register are read into the data buffer. finally, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.3 interrupt reception and return instruction (reti) when an interrupt is received, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. when a return instruction is executed, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.4 address stack manipulation instructions (push ar, pop ar) when a push instruction is executed, the value of the stack pointer is decremented by one, after which the contents of the address register are transferred to the address stack register specified with the stack pointer. when a pop instruction is executed, the contents of the address stack register specified with the stack pointer are transferred to the address register, after which the value of the stack pointer is incremented by one. 3.4.5 system call instruction (syscal entry) and return instruction (ret or retsk) when a syscal entry instruction is executed, the value of the stack pointer is decremented by one, after which the return address and the value of the segment register are stored in the address stack register specified with the stack pointer. when a return instruction is executed, the contents of the address stack register specified with the stack pointer are restored into the program counter and segment register, after which the value of the stack pointer is incremented by one. 3.5 notes on use of address stack 3.5.1 nesting level when the stack pointer contains 0ch, it specifies address stack register asr12, whose value is undefined. if the user attempts to use subroutine calls or interrupts that exceed 12 levels, without stack manipulation, the program will resume from an undefined address. therefore, do not attempt such an operation.
38 m pd17068 4. data memory (ram) 4.1 outline of data memory fig. 4-1 outlines the data memory. as shown in fig. 4-1, the data memory consists of a general-purpose data memory, system registers, data buffer, and port registers. the data memory is used to store data, transfer data to and from peripheral hardware, set display data, transfer data to and from ports, and control the cpu. fig. 4-1 outline of data memory column address 0123456789abcdef data buffer 0 1 2 3 4 5 6 7 port register port register port register port row address bank 0 bank 1 bank 2 system register port register peripheral hardware data transfer data memory data transfer
39 m pd17068 4.2 configuration and functions of data memory fig. 4-2 shows the configuration of the data memory. as shown in fig. 4-2, the data memory is divided into banks. each bank consists of 128 nibbles made up of row addresses 0h to 7h by column addresses 0h to fh. the data memory is divided into the functional blocks described in sections 4.2.1 through 4.2.6 . by using data memory manipulation instructions, 4-bit operations, comparison, decision, and transfer operation can be performed for the data memory. table 4-1 indicates the data memory manipulation instructions. 4.2.1 system register (sysreg) a system register is allocated at addresses 74h-7fh. a system register is allocated, independently of the banks; each bank contains the same system register at addresses 74h-7fh. see chapter 5 for details. 4.2.2 data buffer (dbf) a data buffer is allocated at addresses 0ch-0fh of bank0. see chapter 9 for details. 4.2.3 vram (video ram) for the idc addresses 00h-3fh of bank2 of the data memory can also be used as a vram for the idc. fig. 4-3 shows the configuration of the vram. the vram consists of vrambank0-vrambankd, that is, 672 16 bits. a vrambank can be specified using the vram select register at addresses 73h of bank2. this area is used when the vramsel flag (rf: address 33h, bit 3) is set to 1. when this area is not used as the vram, this area can be used as an ordinary ram. see chapter 16 for details. 4.2.4 port register a port register is allocated at addresses 70h-73h of bank0 and bank1, and at addresses 6fh and 70h- 72h of bank2. see chapter 10 for details. 4.2.5 general-purpose data memory the general-purpose data memory consists of the data memory other than the system registers and port registers. the general-purpose data memory is made up of 335 nibbles; 112 nibbles of each of bank0 and bank1, and 111 nibbles of bank2. 4.2.6 unmounted data memory the data memory at addresses 30h-3fh of bank2 and some portion of the port registers are not allocated for any purpose. for details of the unmounted data memory area, see section 4.4.2 and chapter 10 .
40 m pd17068 fig. 4-2 configuration of data memory 023 1 4 56 7 89abcdef column address 0 1 3 4 5 6 7 row address 0 1 2 3 4 5 6 7 row address 0123456789abcdef data buffer (dbf) general-purpose register bank 0 port register bank 1 port register port register 0 1 2 3 4 5 6 7 row address 0 1 2 3 4 5 6 7 row address bank 1 b 3 b 2 b 1 b 0 address 1ah of bank0 system register data memory bank0 bank1 bank2 example the same system register is allocated. port register specifies a vram bank. column address (vram when vramsel=1; ordinary ram when vramsel=0) these addresses are not allocated for any purpose. system register (sysreg) system register (sysreg) system register (sysreg) vram area
41 m pd17068 fig. 4-3 configuration of vram 01234567 9 8 abcdef vrambank0-d 0 1 2 3 4 5 6 row address bank 2 system register column address 7 fixed at 0 specifies a vram bank. table 4-1 list of data memory manipulation instructions function instruction operation addition add addc subtraction sub subc logical and or xor comparison ske skge sklt skne transfer mov ld st decision skt skf
42 m pd17068 4.3 data memory addressing fig. 4-4 shows how a data memory address is specified. a data memory address is specified with a bank, row address, and column address. a row address and column address are directly specified with a data memory manipulation instruction. a bank is specified with a bank register. see chapter 5 for details of a bank register. fig. 4-4 data memory addressing bank row address column address b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 data memory address bank register instruction operand 4.4 notes on using data memory 4.4.1 power-on reset upon power-on reset, the contents of the general-purpose data memory are undefined. initialize the general-purpose data memory as required. 4.4.2 notes on unmounted data memory if a data memory manipulation instruction is executed for an address in the unmounted data memory, the operations below are performed. (1) device operation when a read instruction is executed, 0 is read. when a write instruction is executed, no change is made. (2) assembler (as17k) operation normal assembly operation is performed. no error occurs. (3) emulator (ie-17k) operation when a read instruction is executed, 0 is read. when a write instruction is executed, no change is made. no error occurs.
43 m pd17068 5. system register (sysreg) 5.1 outline of system register fig. 5-1 shows where the system registers are located in the data memory, and also outlines the system register. as shown in fig. 5-1, a system register is allocated, independently of the banks; each bank contains the same system register at data memory addresses 74h-7fh. the system registers are allocated in the data memory, so that the system registers can be manipulated using any manipulation instructions. a system register consists of seven types of registers for different functions. fig. 5-1 location on data memory and outline of system registers 0123456789abcdef data memory 0 1 2 3 4 5 6 7 bank 0 bank 1 bank 2 system register address 74h 75h 76h 77h 78h 79h address 7ah 7bh 7ch 7dh 7eh 7fh column address row address register system register (ar) window register (wr) bank register (bank) outline program memory address control data transfer to and from register files data memory bank specification register index register (ix) data memory row address pointer (mp) data memory address modification outline general-purpose register pointer (rp) program status word (psword) general-purpose register addressing operation control
44 m pd17068 5.2 format of system register fig. 5-2 shows the format of the system register. fig. 5-2 format of system register address 74h 75h 76h 77h 78h 79h ar3 ar2 ar1 ar0 wr bank bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data 0 0 00 address 7ah 7bh 7ch 7dh 7eh 7fh system register ixh ixm mph mpl ixl rph rpl psw bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data m p e 00 (ix) (mp) 00 (rp) b c d c m p c y zi x e register system register address register (ar) window register (wr) bank register (bank) symbol register symbol index register (ix) data memory row address pointer (mp) general-purpose register pointer (rp) program status word (psword)
45 m pd17068 5.3 address register (ar) 5.3.1 format of address register fig. 5-3 shows the format of the address register. as shown in fig. 5-3, the address register consists of the 16 bits of 74h-77h (ar3-ar0) of a system register. however, the higher 2 bits are always set to 0, so that the address register actually operates as a 14-bit register. fig. 5-3 format of address register remark power-on : at power-on reset clock stop : at clock stop instruction execution ce : at ce reset address 74h 75h 76h 77h address register (ar) ar3 ar2 ar1 ar0 bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data 0 0 upon reset power-on clock stop ce 0000 0000 0000 m s b l s b register symbol
46 m pd17068 5.3.2 address register functions the address register is used to specify program memory addresses for execution of a table reference instruction (movt dbf, @ar), stack manipulation instructions (push ar and pop ar), indirect branch instruction (br @ar), and indirect subroutine call instruction (call @ar). for the address register, a dedicated instruction (inc ar) is available which can increment the address register by 1 at a time. the operation performed when each instruction is executed is described (1) through (5) below. (1) table reference instruction (movt dbf, @ar) the instruction loads the constant data (16 bits) held at the program memory address specified in the address register into the data buffer. constant data stored at addresses 0000h-2fffh can be specified using the address register. (2) stack manipulation instructions (push ar, pop ar) when the push ar instruction is executed, the stack pointer is decremented by 1, then the contents of the address register (ar) are stored in the address stack register pointed to by the decremented stack pointer. when the pop ar is executed, the contents of the address stack register pointed to by the stack pointer are transferred to the address register, then the stack pointer is incremented by 1. (3) indirect branch instruction (br @ar) the instruction causes a branch to the program memory address specified by the address register. a branch address from 0000h to 2fffh can be specified using the address register. (4) indirect subroutine call instruction (call @ar) the subroutine at the program memory address specified by the address register can be called. a subroutine start address from 0000h to 2fffh can be specified by the address register. (5) address register increment instruction (inc ar) the instruction increments the address register by 1. the address register consists of 14 bits. when the inc ar instruction is executed, however, the address register operates on a 13-bit basis. this means that the address specified after 1fffh is not 2000h but 0000h. to increment the address register to 2000h, segment register switching is required. note, however, that the address specified after 3fffh is not 2000h but 0000h; in this case, segment register switching is not required. 5.3.3 address register and data buffer the address register allows data transfer through the data buffer as part of peripheral hardware. see chapter 9 for details. 5.3.4 notes on using address register the address register consists of 14 bits, so that it can specify up to 3fffh. however, the program memory area consists of addresses 0000h-1effh and addresses 2000h-2fffh. accordingly, a value from 0000h to 1effh or from 2000h to 2fffh must be specified in the address register.
47 m pd17068 5.4 window register (wr) 5.4.1 format of window register fig. 5-4 shows the format of the window register. as shown in fig. 5-4, the window register consists of the 4 bits of 78h of a system register. fig. 5-4 format of window register 5.4.2 window register functions the window register is used to transfer data to and from a register file (rf) described later. for data transfer to and from a register file, the dedicated instructions peek wr, rf and poke rf, wr are used (rf: register file address). the operation performed when each instruction is executed is described in (1) and (2) below. see also chapter 8 . (1) peek wr, rf instruction the instruction transfers the contents of the register file addressed by rf to the window register. (2) poke rf, wr instruction the instruction transfers the contents of the window register to the register file addressed by rf. address 78h window register (wr) wr b 3 b 2 b 1 b 0 bit data upon reset power-on clock stop ce l s b m s b symbol register the previous state is held. undefined
48 m pd17068 5.5 bank register (bank) 5.5.1 format of bank register fig. 5-5 shows the format of the bank register. as shown in fig. 5-5, the bank register consists of the 4 bits of 79h (bank) of a system register. however, the higher 2 bits are always set to 0, so that the bank register actually operates as a 2-bit register. fig. 5-5 format of bank register 5.5.2 bank register functions the bank register specifies a data memory bank. table 5-1 indicates the bank register values and specified data memory banks. a bank register is contained in each system register, so that it can be rewritten regardless of the bank currently specified. this means that bank register manipulation is independent of the state of the currently specified bank. table 5-1 data memory bank specification bank register (bank) b 3 b 2 b 1 b 0 0 0 0 0 bank0 0 0 0 1 bank1 0 0 1 0 bank2 0 0 1 1 not to be set data memory bank address 79h bank register (bank) bank bit b 3 b 2 b 1 b 0 data 0 0 m s b l s b upon reset power-on clock stop ce 0 0 0 register symbol
49 m pd17068 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) 5.6.1 index register (ix) (1) format of index register fig. 5-6 shows the format of the index register. the index register consists of 11 bits: the lower 3 bits (ixh) of 7ah of the system register, 7bh (ixm), and 7ch (ixl). the lower 2 bits (bits 2 and 1 of 7ah) are always set to 0. in operation to access the vram, however, only the higher 1 bit (bit 2 of 7ah) is always set to 0. for the method of vram access, see section 16.5.7 . fig. 5-6 format of index register (2) index register functions the index register is used to modify data memory addresses when a data memory manipulation instruction is executed. that is, the data memory bank, row address, and column address specified by a data memory manipulation instruction are ored with the contents of the index register, and the instruction is executed for the data memory location specified by the result of or operation. note, however, that address modification is enabled only when the ixe flag (bit 0 of 7fh of the system register) is set to 1. a dedicated instruction (inc ix) for incrementing the index register allows easy access to a data memory location. address modification using the index register can be performed with all data memory manipulation instructions. with the instructions listed below, address modification using the index register is impossible. address 7ah 7bh 7ch 7eh 7fh index register (ix) memory pointer (mp) ixh ixm mph mpl ixl bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data memory access vram access m p e i x e m p e i x e upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 register symbol psw program status word (psword) fixed at 0 fixed at 0 fixed at 0 vrambank row address column address column address row address bank ix ix
50 m pd17068 inc ar rorc r inc ix call addr movt dbf, @ar call @ar push ar ret pop ar retsk peek wr, rf reti poke rf, wr ei get dbf, p di put p, dbf stop s br addr halt h br @ar nop for details of address modification, see chapter 7 . 5.6.2 data memory row address pointer (mp) (1) format of data memory row pointer fig. 5-7 shows the format of the data memory row address pointer (referred to as the memory pointer). the memory pointer consists of 7 bits: the lower 3 bits (mph) of 7ah of the system register, and 7bh (mpl) of the system register. the higher 2 bits (bits 2 and 1 of 7ah) are always set to 0. in operation to access the vram, however, only the higher 1 bit (bit 2 of 7ah) is always set to 0. for the method of vram access, see section 16.5.7 . (2) memory pointer functions when the general-purpose register indirect transfer instructions (mov @r,m and mov m,@r) are executed, the memory pointer is used to modify the indirect transfer destination address @r. that is, the bank and row address of the indirect transfer destination specified by an instruction is replaced with the contents of the memory pointer. note, however, that address modification is enabled only when the mpe flag (bit 3 of 7ah of the system register) is set to 1. address modification using the memory pointer can be performed only with the general-purpose register indirect transfer instructions.
51 m pd17068 fig. 5-7 format of data memory row address pointer address 7ah 7bh 7ch 7eh 7fh index register (ix) memory pointer (mp) program status word (psword) ixh ixm mph mpl psw bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data memory access m p e i x e vram access m p e i x e upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 register symbol fixed at 0 fixed at 0 fixed at 0 mp bank row address vrambank row address mp ixl
52 m pd17068 5.7 general-purpose register pointer (rp) 5.7.1 format of general-purpose register pointer fig. 5-8 shows the format of the general-purpose register pointer. as shown in fig. 5-8, the general-purpose register pointer consists of 7 bits: the 4 bits of address 7dh (rph) of the system register, and the higher 3 bits of address 7eh (rpl) of the system register. however, the higher 2 bits of address 7dh are always set to 0, so that the lower 5 bits (lower 2 bits of address 7dh and higher 3 bits of address 7eh) are usable. fig. 5-8 format of general-purpose register pointer address 7dh 7eh general-purpose register pointer (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 bit data 0 0 m s b l s b b c d upon reset power-on clock stop ce 0 0 0 0 0 0 register symbol
53 m pd17068 5.7.2 general-purpose register pointer functions the general-purpose register pointer specifies a general-purpose register in the data memory. fig. 5-9 shows the address of a general-purpose register specified with the general-purpose register pointer. as shown in fig. 5-9, the higher 4 bits (rph: address 7dh) of the general-purpose register pointer specify a bank, and the lower 3 bits (rpl: address 7eh) of the general-purpose register pointer specify a row address. the effective bits of the general-purpose register pointer are the five bits, so that any row address (0h-7h) of any bank can be specified as a general-purpose register. however, when the vramsel flag (rf: 33h, bit 3) is set to 1, the vram area and 40h-6fh of bank2 cannot be specified as general-purpose registers. see chapter 6 for details of general-purpose register operation. fig. 5-9 general-purpose register addresses specified by general-purpose register pointer 5.7.3 notes on using general-purpose register pointer the low-order bit of address 7eh (rpl) of the general-purpose register pointer is used as the bcd flag of the program status word. pay attention to the value of the bcd flag when rewriting rpl. general-purpose register pointer (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 00 m s b l s b b c d bank row address 0h 1h 2h 3h bank0 bank2 4h 5h 6h 7h 00 000 00 000 01 000 10 000 11 101 00 101 01 101 10 101 11 specifies a row address. specifies a bank.
54 m pd17068 5.8 program status word (psword) 5.8.1 format of program status word fig. 5-10 shows the format of the program status word. as shown in fig. 5-10, the program status word consists of 5 bits: the low-order bit of 7eh (rpl) of the system register, and the 4 bits of address 7fh (psw) of the system register. a different function is assigned to each bit of the program status word; the program status word consists of a bcd flag (bcd), compare flag (cmp), carry flag (cy), zero flag (z), and index enable flag (ixe). fig. 5-10 format of program status word address 7eh 7fh (rp) program status word (psword) rpl psw bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 data b c d c m p c y zi x e upon reset power-on clock stop ce 0 0 0 0 0 0 register symbol
55 m pd17068 5.8.2 program status word functions the program status word is used to set conditions for transfer instructions and operations by the arithmetic logic unit (alu), and also to indicate the states of the results of operations. table 5-2 outlines the function of each flag of the program status word. see chapter 7 for details. table 5-2 outline of function of each flag of program status word flag name function index enable flag used to specify whether a data memory address is to be (ixe) modified when a data memory manipulation instruction is executed. 0 : not modified 1 : modified zero flag used to indicate that the result of an arithmetic (z) operation is 0. note that the states of 0 and 1 differ, depending on the value of the compare flag. carry flag used to indicate the occurrence of a carry or borrow as (cy) the result of an addition or subtraction instruction executed. this flag is reset to 0 when neither a carry nor a borrow is produced. this flag is set to 1 when a carry or borrow is produced. this flag is used also as a shift bit for the rorc r instruction. compare flag used to specify whether to store the result of an (cmp) arithmetic operation in a data memory area or general- purpose register. 0 : stores the result. 1 : does not store the result. bcd flag used to specify whether to perform an arithmetic (bcd) operation in decimal. 0 : performs a binary operation. 1 : performs a decimal operation. (rp) program status word (psword) rpl psw b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b c d c m p c y zi x e
56 m pd17068 5.8.3 notes on using program status word when an arithmetic instruction (addition or subtraction) is executed for the program status word, the result of the arithmetic operation is stored. if an operation is performed which produces the result 0000b with a carry, for example, 0000b is stored in the psw. 5.9 notes on using system register those data items in the program status word that are always set to 0 are not affected by an attempt to execute a write instruction. when those data items in the program status word that are always set to 0 are read, 0 is read.
57 m pd17068 6. general-purpose register (gr) 6.1 outline of general-purpose register fig. 6-1 outlines the general-purpose register. as shown in fig. 6-1, the general-purpose register consists of a general-purpose register pointer and general-purpose register body. the bank and row address of a general-purpose register body is specified with the general-purpose register pointer. a general-purpose register pointer body is used to perform an operation with or transfer data to and from a data memory area. fig. 6-1 outline of general-purpose register 6.2 general-purpose register body the general-purpose register body consists of a row on the data memory, which is 16 nibbles (16 4 bits) long. see section 5.7 for information about the general-purpose register pointer, and a bank and row address specifiable as a general-purpose register. one instruction can be used to perform an operation with or transfer data to and from a 16-nibble row specified as a general-purpose register. this means that an operation or data transfer between data memory areas can be performed with one instruction. as with other data memory areas, a general-purpose register can be controlled using data memory manipulation instructions. column address data memory general-purpose register row address general-purpose register pointer bank0 bank1 bank2 system register transfer, operation
58 m pd17068 6.3 general-purpose register address generation with instructions sections 6.3.1 and 6.3.2 below describe general-purpose register address generation when each instruction is executed. for the detailed operation of each instruction, see chapter 7 . 6.3.1 addition instructions (add r,m, addc r,m) subtraction instructions (sub r,m, subc r,m) logical operation instructions (and r,m, or r,m, xor r,m) direct transfer instructions (ld r,m, st m,r), and rotate instruction (rorc r) table 6-1 indicates a general-purpose register address specified by operand r of an instruction. operand r specifies only a column address. table 6-1 general-purpose register address generation bank row address column address b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 2 b 1 b 0 b 3 r contents of general- purpose register pointer general-purpose register address 6.3.2 indirect transfer instructions (mov @r,m, mov m,@r) table 6-2 indicates a general-purpose register address specified by operand r of an instruction, and an indirect transfer address specified by @r. table 6-2 general-purpose register address generation bank row address column address b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 2 b 1 b 0 b 3 r contents of general- purpose register pointer same as data memory contents of r general-purpose register address indirect transfer address
59 m pd17068 6.4 notes on using general-purpose register 6.4.1 row address of general-purpose register the row address of a general-purpose register is specified by the general-purpose register pointer. accordingly, note that the currently specified bank may differ from the bank of the general-purpose register specified. 6.4.2 operation between general-purpose register and immediate data no instruction is available for operation between a general-purpose register and immediate data. to execute an operation instruction between a general-purpose register and immediate data, the general- purpose register area must be handled as a data memory area.
60 m pd17068 7. arithmetic logic unit (alu) block 7.1 overview fig. 7-1 is an overview of the alu block. as shown in fig. 7-1, the alu block consists of the alu, temporary storage registers a and b, program status word, decimal conversion circuit, and data memory address controller. the alu performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. fig. 7-1 overview of the alu block data memory data bus program status word address controller temporary storage register a temporary storage register b indexing memory pointer detecting a carry, borrow, or zero setting decimal calculation or result storage alu ? arithmetic operation ? logic operation ? bit discrimination ? comparative discrimination ? rotation ? transfer decimal conversion
61 m pd17068 7.2 configuration and functions of the components of the alu block 7.2.1 alu in response to a programmed instruction, the alu performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 temporary storage registers a and b temporary storage registers a and b temporarily hold the 4-bit data. these registers are automatically used when an instruction is executed. they cannot be controlled by a program. 7.2.3 program status word a program status word controls the operation of the alu and holds the status of the alu. for details of the program status word, see section 5.8 . 7.2.4 decimal conversion circuit if the bcd flag of the program status word is set to 1 when an arithmetic operation is executed, the decimal conversion circuit converts the results of the arithmetic operation to a decimal number. 7.2.5 address controller the address controller specifies an address in data memory. at the same time, the circuit also controls address modification by the index register or data memory row address pointer. 7.3 alu operations table 7-1 lists the operations performed by the alu when instructions are executed. table 7-2 shows the data memory address modification by the index register and data memory row address pointer. table 7-3 lists the converted decimal data used in decimal operations.
62 m pd17068 table 7-1 alu operations alu function addition subtraction logic operation discrimi- nation comparison transfer rotation add addc sub subc or and xor skt skf ske skne skge sklt ld st mov rorc r r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r, m m, r m, #n4 @r, m m, @r 00 01 10 11 instruction operation difference due to program status word (psword) address modification value of the bcd flag value of the cmp flag operation operation of the cy flag operation of the z flag index memory pointer optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (reset) binary operation the result is stored. binary operation the result is not stored. decimal operation the result is stored. decimal operation the result is not stored. not changed not changed not changed not changed not changed set by a carry or borrow. otherwise, the flag is reset. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. value of b 0 of the general- purpose register retains the previous state. set if the operation result is 0000b. otherwise, the flag is reset. set if the operation result is 0000b. otherwise, the flag is reset. retains the status if the operation result is 0000b. otherwise, the flag is reset. retains the status if the operation result is 0000b. otherwise, the flag is reset. provided not provided provided not provided provided not provided provided provided not provided not provided provided not provided not provided
63 m pd17068 table 7-2 modification of the data memory address and indirect transfer address by the index register and data memory row address pointer b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ixe mpe 00 01 10 11 rp r bank m bank m r (r) (r) mp bank m bank m r (r) mp (r) ixh, ixm ix logical or general-purpose register address specified with r data memory address specified with m indirect transfer address specified with @r bank row address column address bank row address column address bank row address column address same as above same as above same as above same as above same as above logical or bank : bank register ix : index register ixe : index enable flag ixh : bits 10 to 8 of the index register ixm : bits 7 to 4 of the index register ixl : bits 3 to 0 of the index register m : data memory address specified with m r and m c m r : data memory row address (high order) m c : data memory column address (low order) mp : data memory row address pointer mpe : memory pointer enable flag r : general-purpose register column address rp : general-purpose register pointer (x) : contents addressed by x x : m, r, and other direct address
64 m pd17068 table 7-3 converted decimal data operation result hexadecimal addition 0 0 0000b 0 0000b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 10 0 1010b 1 0000b 11 0 1011b 1 0001b 12 0 1100b 1 0010b 13 0 1101b 1 0011b 14 0 1110b 1 0100b 15 0 1111b 1 0101b 16 1 0000b 1 0110b 17 1 0001b 1 0111b 18 1 0010b 1 1000b 19 1 0011b 1 1001b 20 1 0100b 1 1110b 21 1 0101b 1 1111b 22 1 0110b 1 1100b 23 1 0111b 1 1101b 24 1 1000b 1 1110b 25 1 1001b 1 1111b 26 1 1010b 1 1100b 27 1 1011b 1 1101b 28 1 1100b 1 1010b 29 1 1101b 1 1011b 30 1 1110b 1 1100b 31 1 1111b 1 1101b operation result decimal addition cy cy operation result 0 0 0000b 0 0000b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 10 0 1010b 1 1100b 11 0 1011b 1 1101b 12 0 1100b 1 1110b 13 0 1101b 1 1111b 14 0 1110b 1 1100b 15 0 1111b 1 1101b C16 1 0000b 1 1110b C15 1 0001b 1 1111b C14 1 0010b 1 1100b C13 1 0011b 1 1101b C12 1 0100b 1 1110b C11 1 0101b 1 1111b C10 1 0110b 1 0000b C9 1 0111b 1 0001b C8 1 1000b 1 0010b C7 1 1001b 1 0011b C6 1 1010b 1 0100b C5 1 1011b 1 0101b C4 1 1100b 1 0110b C3 1 1101b 1 0111b C2 1 1110b 1 1000b C1 1 1111b 1 1001b operation result hexadecimal subtraction operation result decimal subtraction cy cy operation result remark correct decimal conversion is not possible in the shaded area.
65 m pd17068 7.4 notes on using the alu 7.4.1 notes on using the program status word for operations after an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. the cy and z flags of the program status word are usually set or reset according to the result of the arithmetic operation. if the arithmetic operation is performed on the program status word itself, the result of the operation is stored and a carry, borrow, or zero cannot be discriminated. if the cmp flag is set, the result of the arithmetic operation is not stored and the cy and z flags are set or reset as usual. 7.4.2 notes on performing decimal operations a decimal operation can be carried out only when the operation result is within the following ranges: (1) the result of addition is between 0 and 19 in decimal. (2) the result of subtraction is between 0 and 9 or C10 and C1 in decimal. if a decimal operation exceeding the above ranges is performed, the cy flag is set, resulting in a value greater than or equal to 1010b (0ah).
66 m pd17068 8. register file (rf) 8.1 overview fig. 8-1 shows an overview of the register file. as shown in fig. 8-1, the register file consists of control registers in a different space from data memory, and a part of data memory. the control register sets the conditions of the peripheral hardware. the data in the register file is read and written through a window register. fig. 8-1 overview of the register file register file control registers (different space from data memory) 0 1 2 3 4 5 6 7 row address system register window register peripheral hardware (configured in data memory) data manipulation through the window register
67 m pd17068 8.2 configuration and functions of the register file fig. 8-2 shows the configuration of the register file and the relationship between the register file and data memory. like data memory, the register file is assigned addresses in units of four bits. the row addresses range from 0h to 7h and the column addresses from 0h to 0fh, that is, 128 nibbles in total. the address locations from 00h to 3fh are referred to as control registers and are used to set the conditions for the peripheral hardware. address locations 40h to 7fh and data memory overlap. the data at addresses 40h to 7fh in the register file is identical to that at addresses 40h to 7fh in the current bank of data memory. because address locations 40h to 7fh and data memory overlap, they are the same as the ordinary address locations in data memory, except that they can be manipulated by the register file manipulation instructions (peek wr, rf and poke rf, wr). fig. 8-2 configuration of the register file and the relationship between the register file and data memory column address 0123456789abcdef 0 1 2 3 4 5 6 7 row address 0 1 2 3 data memory bank0 bank1 bank2 system register control register register file
68 m pd17068 8.2.1 register file manipulation instructions (peek wr, rf and poke rf, wr) data in the register file is read and written through the window register of the system register. the following instructions are used: (1) peek wr, rf reads the data at address rf of the register file into the window register. (2) poke rf, wr writes the data of the window register at address rf into the register file. 8.3 control registers fig. 8-3 shows the configuration of the control registers. as shown in fig. 8-3, the control registers consist of 64 nibbles (64 x 4 bits) of addresses 00h to 3fh in the register file. however, only 61 nibbles are actually used. the remaining three nibbles are not used, reading and writing for these nibbles being inhibited. each nibble of each control register has an attribute. each nibble has one of the following four attributes: read/write (r/w), read only (r), write only (w), and reset at reading (r & reset). if writing to a read-only (r, or r & reset) register is attempted, nothing changes. if reading from a write-only (w) register is attempted, an undefined value is read. of the four bits in a single nibble, a bit that is always set to 0 is always read as 0. even if writing is attempted, the bit remains set to 0. if an attempt is made to read the contents of the three unused nibbles, an undefined value is read. if writing to the unused part is attempted, nothing changes.
69 m pd17068 [memo]
70 m pd17068 fig. 8-3 configuration of the control registers (1/2) note an address used with the assembler (as17k) is indicated in parentheses. column address row address item 0 1 2 3 4 5 6 7 0 (8) note stack pointer (sp) s p 3 ( s p 2 ( s p 1 ( s p 0 ( 000 c e e d e t 000 p w m 8 s e l p w m 7 s e l p w m 6 s e l p w m 5 s e l p w m 4 s e l p w m 3 s e l p w m 2 s e l p w m 1 s e l p w m 0 s e l w t m h l d 0 c k o s e l x t s e l 000 c e read/ write r/w r & reset r/w r/w r/w w r / w r 1 (9) note 0 h s c g t 1 0 h s c g t 0 h s c g o s t t 000 p l l r f c k 3 p l l r f c k 2 p l l r f c k 1 p l l r f c k 0 w t m r e s 3 w t m r e s 2 w t m r e s 1 w t m r e s 0 0 i n t n c m d 2 i n t n c m d 1 i n t n c m d 0 000 b t m 1 c y 000 b t m 0 c y read/ write r/w r r/w r/w r/w r & reset r & reset 2 (a) note 0 r l s e n 0 00 a d c c h 2 a d c c h 1 a d c c h 0 000 p l l u l a d c e n 00 a d c c m p 0 p 2 d b i o 2 p 2 d b i o 1 p 2 d b i o 0 000 p 1 c g i o read/ write r/w r & reset r r/w r/w r/w r/w read/ write r/w r /w r & reset r/w r/w r/w r/w r/w 3 (b) note i d c b k e n 0 i d c b k r i d c b k g i d c b k b 00 i d c e n0 0 p l u l s e n 1 p l u l s e n 0 v r a m s e l i d c s e l i d c d 1 4 s l i d c c p c h 000 p 1 b 2 e d e t p 1 b b i o 3 p 1 b b i o 2 p 1 b b i o 1 p 1 b b i o 0 p 0 b b i o 3 p 0 b b i o 2 p 0 b b i o 1 p 0 b b i o 0 p 0 a b i o 3 p 0 a b i o 2 p 0 a b i o 1 p 0 a b i o 0 register ce pin edge detection register pwm mode select register 3 pwm mode select register 2 pwm mode select register 1 watch timer mode select register ce pin level judge register symbol h sync - counter-gate control register h sync - counter-gate judge register register symbol pll refer- ence clock select register int nc mode select register basic timer 1 carry flip-flop judge register basic timer 0 carry flip-flop judge register watch timer reset register register symbol clock-stop release enable register a/d converter channel select register pll-unlock- flip-flop judge register a/d converter control register port 2d bit i/o select register port 1c group i/o select register idc back- ground select register register symbol idc enable register pll-unlock- flip-flop sensibility select register idc mode select register p1b 2 pin edge detection register port 1b bit i/o select register port 0b bit i/o select register port 0a bit i/o select register
71 m pd17068 fig. 8-3 configuration of the control registers (2/2) 89 a b c d e f s i o 0 c h s b s i o 0 m s s i o 0 t x 000 t m 0 c k b t m 2 c k 1 b t m 2 c k 1 b t m 1 c k 1 b t m 1 c k 0 b t m 0 c k 1 b t m 0 c k 0 0 t m o e n0 00 t m 0 v f0 i g r p 1 s l i g r p 0 s l r/w r/w r/w r/w r/w r/w 00 t m 1 c k 1 t m 1 c k 0 t m 1 r e s t m 1 e n 00 s i o 1 t s s i o 1 h i z s i o 1 c k 1 s i o 1 c k 0 000 w t m 8 h z 000 w t m 1 2 8 h z 0 i e g g r p 1 i e g 0 i e g n c b t m 2 e x c k b t m 2 z x b t m 1 e x c k b t m 1 z x 00 t m 0 r p t t m 0 r e s 0 w r / w r r/w s b a c k s i o 0 n w t s i o 0 w r q 1 s i o 0 w r q 0 r/w r/w r/w w r / w r/w r & reset r & reset r/w 0 s i o 0 s f 8 s i o 0 s f 9 s b s t t s b b s y00 i r q g r p 0 000 i r q s i o 1 00 i r q s i o 0 00 i r q g r p 1 0 i n t g r p 1 00 i p g r p 0 i p s i o 1 i p s i o 0 i p g r p 1 i p i d c v p i p b t m 2 i p t m 1 i p t m 0 i p 0 i p n c r r/w r/w r/w r r/w r/w r/w r/w 0 s i o 0 i m d 0 0 s i o 0 i m d 1 00 s i o 0 c k 1 s i o 0 c k 0 000 i r q i d c v p 000 i r q b t m 2 000 i r q t m 1 00 i r q t m 0 i n t 0 00 0 i r q 0 i n t n c00 i r q n c r/w r/w r/w r/w r/w r/w r r/w r r/w serial i/o 0 mode select register timer 0 clock select register basic timer 2 mode select register basic timer 1 mode select register basic timer 0 clock select register timer 0 control register timer 0 overflow register interrupt group selection register serial i/o 0 wait control register timer 1 clock select register timer 1 control register serial i/o 1 mode select register watch timer 8-hz carry register watch timer 128-hz carry register interrupt edge selection register serial i/o 0 status judge register interrupt request register 10 interrupt request register 8 interrupt request register 7 interrupt enable register 3 interrupt request register 9 interrupt enable register 2 interrupt enable register 1 serial i/o 0 interrupt mode register serial i/o 0 clock select register interrupt request register 6 interrupt request register 5 interrupt request register 4 interrupt request register 3 interrupt request register 2 interrupt request register 1
72 m pd17068 table 8-1 peripheral hardware control functions of the control registers (1/7) remark h: holds the previous state. read/ write 01h r/w b 3 b 2 b 1 b 0 (sp3) (sp2) (sp1) (sp0) wtmhld 0 ckosel xtsel w 06h 0 0 0 tm0ck r/w 09h btm2exck btm2zx btm2ck1 btm2ck0 r/w 0ah btm1exck btm1zx btm1ck1 btm1ck0 r/w 0bh 0 0 btm0ck1 btm0ck0 r/w 0ch 0 tm0rpt tm0res tm0en r/w 0dh w r/w 0 0 0 tm0ovf wtmres3 wtmres2 wtmres1 wtmres0 r 0eh r/w 14h peripheral hardware control register peripheral hardware control function upon reset register address symbol function overview set value p o w e r o n s t o p c e 01 stack timer stack pointer (sp) watch timer mode register timer 0 clock select register basic timer 2 mode select register basic timer 1 mode select register basic timer 0 mode select register timer 0 control register timer 0 overflow register watch timer reset register stack pointer selects whether to hold the watch timer for 500 ms. always set to 0. selects whether to output an oscillation frequency of 32.768 khz. selects the function of the p0d 1 and p0d 0 pins. always set to 0. sets the clock of timer 0. selects the base clock (internal/ external). turns the zero-cross circuit on or off. sets an interrupt time. selects the operation mode of timer 0. selects the base clock (internal/ external). turns the zero-cross circuit on or off. sets a carry flip-flop time. always set to 0. sets a carry flip-flop time. always set to 0. selects whether to reset the timer 0 counter. selects whether to start the timer 0 counter. always set to 0. detects whether the timer 0 counter overflows. selects whether to reset the watch timer. does not hold. does not output. operates as a port. 0, 4: 100 ms 1,5: 5 ms 2,6: 1 ms 3,7: 125 s 8, 9: divides the external clock by 5. a, b: divides the external clock by 6. c, d: divides the external clock by 5 (with zero-cross on). e, f: divides the external clock by 6 (with zero-cross on). 10 s 50 s 0, 4: 100 ms 1,5: 5 ms 2,6: 1 ms 3,7: 125 s 8, 9: divides the external clock by 5. a, b: divides the external clock by 6. c, d: divides the external clock by 5 (with zero-cross on). e, f: divides the external clock by 6 (with zero-cross on). 0 0 0 0 0 0 0 0 100 ms 5 ms 1 ms 1 ms holds. outputs. free-run count mode modulo count mode connects an oscillator. does not perform reset. does not start. does not overflow. does not reset. resets. starts. overflows. resets. 12 12 12 hh hh 000 00h 00h 00h 00h 00h 00h 0hh r/w
73 m pd17068 table 8-1 peripheral hardware control functions of the control registers (2/7) 0 0 0 btm1cy r & res 16h 0 0 0 btm0cy r & res 17h 0 0 tmck1 tmck0 r/w 1ah 0 0 tm1res tm1en r/w 1bh w r/w 0 0 0 wtm8hz r & res 1dh 0 0 0 wtm128hz r & res 1eh 0 0 igrp1sl igrp0sl 0fh r/w 0 intncmd2 intncmd1 intncmd0 15h r/w 0 ieggrp1 ieg0 iegnc 1fh r/w timer interrupt basic timer 1 carry flip-flop judge register read/ write b3 b2 b1 b0 peripheral hardware control register peripheral hardware control function upon reset register address symbol function overview set value p o w e r o n s t o p c e 01 basic timer 0 carry flip-flop judge register timer 1 clock select register timer 1 control register watch timer 8-hz carry register watch timer 128-hz carry register interrupt group selection register int nc mode select register interrupt edge selection register always set to 0. detects the status of the carry flip-flop. always set to 0. detects the status of the carry flip-flop. always set to 0. sets the clock of timer 1. always set to 0. selects whether to reset the timer 1 counter. selects whether to operate the timer 1 counter. always set to 0. detects the status of the carry flip-flop. always set to 0. detects the status of the carry flip-flop. always set to 0. selects an interrupt source (group 1). timer 0 overflow interrupt (group 0) always set to 0. selects the pulse width used for accepting the interrupt of the int nc pin. always set to 0. sets the edge where an interrupt is issued (group 1). sets the edge where an interrupt is issued (int 0 ). sets the edge where an interrupt is issued (int nc ). reset set reset set 00 1 1 01 0 1 1 ms 100 ? 50 ? 10 ? does not perform reset. resets. does not start. starts. v sync signal h sync signal reset set reset set is not used. is used. 0 : accepts at the edge. 1 : 200 s 2 : 400 s 3 : 2 ms 4 : 4 ms rising edge falling edge 01 1 01 1 00 h 00 h 0h h 0h h 00 0 00 0 00 0 remark h: holds the previous state.
74 m pd17068 table 8-1 peripheral hardware control functions of the control registers (3/7) 0 0 0 irqgrp0 r/w 2ah 0 0 0 irqsio1 r/w 29h 0 0 0 irqsio0 2bh r/w intgrp1 0 0 irqgrp1 r r/w 2ch 0 0 0 irqidcvp r/w 3ah 0 0 0 irqbtm2 r/w 3bh 0 0 0 irqtm1 r/w 3ch r/w 3dh 0 0 0 irqtm0 r int0 0 0 irq0 r/w 3eh interrupt request register 10 read/ write b3 b2 b1 b0 peripheral hardware control register peripheral hardware control function upon reset register address symbol function overview set value p o w e r o n s t o p c e 01 interrupt request register 9 interrupt request register 8 interrupt request register 7 interrupt request register 6 interrupt request register 5 interrupt request register 4 interrupt request register 3 interrupt request register 2 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 interrupt always set to 0. detects an interrupt request (group 0). always set to 0. detects an interrupt request (sio 1 ). always set to 0. detects an interrupt request (sio 0 ). displays the level of the h sync /v sync signal. always set to 0. always set to 0. always set to 0. always set to 0. always set to 0. always set to 0. displays an interrupt request (group 1). detects an interrupt request (vram pointer). detects an interrupt request (btm2). detects an interrupt request (tm1). detects an interrupt request (tm0). detects an interrupt request (int 0 pin). displays the level of the signal input to the int 0 pin. low level high level detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. low level high level detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. detects no interrupt request or interrupt handling is in progress. detects an interrupt request. low level high level
75 m pd17068 table 8-1 peripheral hardware control functions of the control registers (4/7) r intnc 0 0 irqnc r/w 3fh 0 0 ipgrp0 ipsi01 r/w 2dh ipsio0 ipgrp1 ipidcvp ipbtm2 r/w 2eh iptm1 iptm0 ip0 ipnc r/w 2fh 0 0 0 ceedet r & res 02h 0 0 0 ce r 07h 0 0 0 rlsen r/w 20h 0 0 0 p1b2edet r & res 34h pllrfck3 pllrfck2 pllrfck1 pllrfck0 r/w 13h interrupt pin read/ write b3 b2 b1 b0 peripheral hardware control register peripheral hardware control function upon reset address symbol function overview set value p o w e r o n s t o p c e 01 00 0 00 0 00 0 00 0 0 0 0h h 0 ff h pll frequency synthesizer register interrupt request register 1 interrupt enable register 3 interrupt enable register 2 interrupt enable register 1 ce pin edge detection register ce pin level judge register clock-stop release enable register p1b 2 pin edge detection register pll reference clock select register displays the level of the signal input to the int nc pin. always set to 0. always set to 0. always set to 0. always set to 0. always set to 0. always set to 0. detects an interrupt request (int nc pin). group 0 serial interface 1 serial interface 0 group 1 vram pointer basic timer 2 timer 1 timer 0 int0 pin int nc pin selects whether to enable an interrupt. detects the input of a rising edge to the ce pin. detects the status of the ce pin. selects whether to release the clock-stop by the p1b 2 pin. detects the input of a rising edge to the p1b 2 pin. sets the pll reference frequency. low level high level detects no interrupt request or interrupt handling is in progress. detects an interrupt request. inhibits an interrupt. enables an interrupt. does not detect the input. detects the input. does not release. releases. low level high level does not detect the input. detects the input. 2: 5 khz 6: 25 khz 0, 1, 7 to e: setting inhibited 3: 10 khz f: operation stop (disable status) 4: 6.25 khz 5: 12.5 khz remark h: holds the previous state.
76 m pd17068 table 8-1 peripheral hardware control functions of the control registers (5/7) 0 0 0 pllul r & res 22h 0 0 plulsen1 plulsen0 32h r/w 0 adcch2 adcch1 adcch0 21h r/w adcen 0 0 adccmp r r/w 24h 0 p2dbio2 p2dbio1 p2dbio0 r/w 26h 0 0 0 p1cgio r/w 27h p1bbio3 p1bbio2 p1bbio1 p1bbio0 r/w 35h p0bbio3 p0bbio2 p0bbio1 p0bbio0 r/w 36h p0abio3 p0abio2 p0abio1 p0abio0 r/w 37h 0 : adc 0 2 : p0d 1 /adc 2 /xt in 4 : p0d 3 /adc 4 6 : p0c 1 /adc 6 1 : p0d 0 /adc 1 /xt out 3 : p0d 2 /adc 3 5 : p0d 0 /adc 5 6 : p0d 2 /adc 7 v adcin < v ref v adcin > v ref read/ write b3 b2 b1 b0 peripheral hardware control register peripheral hardware control function upon reset address symbol function overview set value p o w e r o n s t o p c e 01 uh h 00 h 00 0 00 0 00 0 00 0 00 0 register pll frequency synthesizer a/d converter general-purpose port pll-unlock- flip-flop judge register pll-unlock- flip-flop sensibility select register a/d converter channel select register a/d converter control register port 2d bit i/o select register port 1c group i/o select register port 1b bit i/o select register port 0b bit i/o select register port 0a bit i/o select register always set to 0. always set to 0. always set to 0. always set to 0. always set to 0. detects the status of the unlock flip-flop. specifies a delay for setting the unlock flip-flop. selects the pins to be used as the a/d converter. sets the operation of the a/d converter. detects the result of comparison. always set to 0. p2d 2 pin p2d 1 pin p2d 0 pin sets the pin for input or output (bit i/o). sets port 1c for input or output (group i/o). p1b 3 pin p1b 2 pin p1b 1 pin p1b 0 pin p0b 3 pin p0b 2 pin p0b 1 pin p0b 0 pin p0a 3 pin p0a 2 pin p0a 1 pin p0a 0 pin sets the pin for input or output (bit i/o). lock status unlock status 0 1.25 0 3.5 0 0.25 1 disable 0 ?.5 s 1 ?.75 s 1 ?.5 s 1 disable stop start uh h input output input output input output remark h: holds the previous state. u: undefined
77 m pd17068 table 8-1 peripheral hardware control functions of the control registers (6/7) b3 b2 b1 b0 0 0 0 03h r/w pwm8sel pwm7sel pwm6sel pwm5sel pwm4sel 04h r/w pwm3sel pwm2sel pwm1sel pwm0sel 05h r/w sio0ch sb sio0ms sio0tx 08h r/w sback sio0nwt sio0wrq1 sio0wrq0 18h r/w sio1ts sio1hiz sio1ck1 sio1ck0 1ch r/w sio0sf8 sio0sf9 sbstt sbbsy 28h r 0 0 sio0imd1 sio0imd0 38h r/w 0 0 sio0ck1 sio0ck0 39h r/w s t o p c e p o w e r o n read/ write peripheral hardware control register peripheral hardware control function upon reset address symbol function overview set value register 01 d/a converter serial interface pwm mode select register 3 pwm mode select register 2 pwm mode select register 1 serial i/o 0 mode select register serial i/o 0 wait control register serial i/o 1 mode select register serial i/o 0 status judge register serial i/o 0 interrupt mode register serial i/o 0 clock select register always set to 0. p2a 0 /pwm 8 pin p2b 3 /pwm 7 pin p2b 2 /pwm 6 pin p2b 1 /pwm 5 pin p2b 0 /pwm 4 pin p2c 3 /pwm 3 pin p2c 2 /pwm 2 pin p2c 1 /pwm 1 pin p2c 0 /pwm 0 pin selects whether to set these pins as a d/a con- verter. sets the number of communi- cation wires. sets the communication method. sets master or slave operation. sets the direction of transfer. sets and detects the acknowledg- ment (i 2 c bus method). selects whether to enable a wait. sets a wait mode. selects whether to start or stop the operation. sets the status of the p2d 1 /so 1 pin. sets the i/o clock. detects the contents of the clock counter. detects the number of clocks (i 2 c bus method). detects the starting conditions (i 2 c bus method). always set to 0. sets the internal clock of serial interface 0. sets the interrupt condition of serial interface 0. always set to 0. general-purpose output port da converter 00u two-wire system three-wire system serial i/o method i 2 c bus method (two- wire system only) master operation reception sets and detects 0 or 1. enables. 0 0 no wait. 0 1 data wait. 1 0 acknow- ledge wait. 1 1 address wait. stops the operation. general-purpose i/o port 0 or 1 0 or 1 up to nine clocks are set, beginning with the start condition. all clocks are set, from the start condition up to the stop condition. 0 0 external clock 0 1 100 khz 1 0 500 khz 1 1 1 khz 0 0 seventh clock 0 1 eighth clock 1 0 7th clock after the start con- dition 1 1 stop condi- tion 0 0 0 1 50 khz 1 0 500 khz 1 1 1 khz 100 khz slave operation transmission releases. starts the operation serial data output pin 000 000 000 000 uhh uhh 8 9 remark h: holds the previous state. u: undefined
78 m pd17068 table 8-1 peripheral hardware control functions of the control registers (7/7) 0 0 hscgt1 hscgt0 r/w 11h hscgostt 0 0 0 r 12h idcbken idcbkr idcbkg idcbkb r/w 30h 0 0 0 idcen r/w 31h vramsel idcisel idcd14sel idccpch r/w 33h b3 b2 b1 b0 s t o p c e p o w e r o n read/ write peripheral hardware control register peripheral hardware control function upon reset address symbol function overview set value register 01 horizontal synchronizing signal counter idc h sync -counter -gate control register h sync -counter- gate judge register idc back- ground select register idc enable register idc mode select register always set to 0. controls the gate of the h sync counter. always set to 0. detects whether the gate of the h sync counter is open or closed. specifies the screen background. background color r background color g background color b eight colors always set to 0. turns the idc display on or off. turns vram on or off. selects the function of the p0b 2 /i pin. sets the number of dots in the vertical direction for the character to be displayed. sets the display interval between characters. 0 0 gate closed 0 1 gate open 1 0 1.69 ms open 1 1 setting inhibited closed open does not display the screen background color. displays the screen background color. 0: black, 1: blue, 2: green, 3: cyan, 4: red, 5: magenta, 6: yellow, 7: white display on display off vram off vram on general-purpose port i pin 16 dots 14 dots no interval interval of 2 dots 000 000 0 000 000
79 m pd17068 8.4 notes on using the register file when operating a write-only (w) register, read-only (r) register, or unused register of the control registers (address locations 00h to 3fh of the register file), note (1), (2), and (3) below: (1) if reading from a write-only register is attempted, an undefined value is read. (2) if writing to a read-only register is attempted, nothing changes. (3) if an attempt is made to read the contents of an unused part, an undefined value will be read. if writing to an unused part is attempted, nothing changes.
80 m pd17068 9. data buffer (dbf) 9.1 overview fig. 9-1 shows an overview of the data buffer. the data buffer is configured in data memory. it provides the following two functions: (1) function to read constant data related to program memory (refer to the table) (2) function to transfer data to or from the peripheral hardware fig. 9-1 overview of the data buffer data buffer writing data (put) referencing a table (movt) reading data (get) peripheral hardware constant data program memory
81 m pd17068 9.2 data buffer main body 9.2.1 configuration of the data buffer main body fig. 9-2 shows the configuration of the data buffer. as shown in fig. 9-2, the data buffer consists of 16 bits of addresses 0ch to 0fh of bank0 in data memory. the most significant bit (msb) of the 16-bit data is bit 3 at address 0ch. the least significant bit (lsb) is bit 0 at address 0fh. the data buffer is configured in data memory and can thus be manipulated by any data memory manipulation instruction. fig. 9-2 configuration of the data buffer 0123456789abcdef data buffer (dbf) data memory bank0 bank1 bank2 system register 7 7 0 1 2 3 4 5 6 7 data memory address 0ch 0dh 0ed 0fh bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 data buffer dbf 3 dbf 2 dbf 1 dbf 0 data m s b l s b bit symbol column address low address data
82 m pd17068 9.2.2 instruction to reference a table (movt dbf, @ar) the movt dbf, @ar instruction functions as described below: when an instruction to reference a table is executed, a stack of a single level is used. all program memory addresses, 0000h to 2fffh, allow table reference. movt dbf, @ar data at the address specified by the address register is read from program memory and placed in the data buffer. 9.2.3 instructions for controlling the peripheral hardware (put, get) the put and get instructions operate as described below: (1) get dbf, p data in the peripheral register at address p is read and written into the data buffer. (2) put p, dbf data in the data buffer is set in the peripheral register at address p. 9.3 peripheral hardware and data buffer table 9-1 lists the functions of the data buffer and peripheral hardware.
83 m pd17068 [memo]
84 m pd17068 table 9-1 relationship between the peripheral hardware and data buffer (1/2) peripheral hardware peripheral register used to transfer data to or from the data buffer name symbol peripheral address instruction that can be used image display controller (idc) idc vram idcorg 01h put/get idcvp 42h get idcvpr 43h put/get adcr 02h put/get sio0sfr 03h put/get sio1sfr 07h hsc 04h get tm1m 05h put/get tm1c 06h get pwmr0 0ch put/get pwmr1 0dh pwmr2 0eh pwmr3 0fh pwmr4 10h pwmr5 11h pwmr6 12h pwmr7 13h pwmr8 14h wtmsec 1ah wtmmin 1bh wtmhr 1ch wtmday 1dh put/get ar 40h put/get pllr 41h put/get tmom 46h put/get tmoc 47h get a/d converter serial interface horizontal synchronizing signal counter timer 1 d/a converter (pwm output) watch timer address register (ar) pll frequency synthesizer timer 0 serial interface 0 (sio 0 ) serial interface 1 (sio 1 ) timer 1 modulo timer 1 counter p2c 0 /pwm 0 pin p2c 1 /pwm 1 pin p2c 2 /pwm 2 pin p2c 3 /pwm 3 pin p2b 0 /pwm 4 pin p2b 1 /pwm 5 pin p2b 2 /pwm 6 pin p2b 3 /pwm 7 pin p2a 0 /pwm 8 pin seconds counter minutes counter hours counter days counter timer 0 modulo timer 0 counter idc start position setting register vram pointer buffer vram pointer register a/d converter data register sio0 shift register sio1 shift register h sync counter data register timer 1 modulo register timer 1 counter pwm data register 0 pwm data register 1 pwm data register 2 pwm data register 3 pwm data register 4 pwm data register 5 pwm data register 6 pwm data register 7 pwm data register 8 seconds setting register minutes setting register hours setting register days setting register address register pll data register timer 0 modulo register timer 0 counter
85 m pd17068 table 9-1 relationship between the peripheral hardware and data buffer (2/2) function number of i/o bits of the data buffer number of bits actually used description 88 16 10 16 10 86 88 86 88 88 88 8 6 5 3 16 14 16 16 16 12 16 12 sets the display start position of the image display controller. specifies a vram address. reads the value of the vram pointer. sets the reference voltage (vref) of the a/d converter. sets the serial out data and reads the serial in data. reads the value of the horizontal synchronizing signal counter. sets the reference data for timer 1. reads the count for timer 1. duty cycle : d = writes and reads the data of the seconds counter, minutes counter, hours counter, and days counter. transfers data to or from the address register. sets n, by which the pll frequency is divided. sets the reference data for timer 0. reads the data of the timer 0 counter. v ref = x ?0.5 64 v dd ,1 x 63 sets the duty cycle of the output signal of the d/a converter. x 256 100%, 0 x 255 frequency : f = 1.953 khz
86 m pd17068 9.4 notes on using the data buffer when transferring data, through the data buffer, to or from the peripheral hardware, note the following three points on unused peripheral addresses, write-only peripheral registers (put only), and read-only peripheral registers (get only): (1) if reading of a write-only register is attempted, an undefined value will be read. (2) if writing to a read-only register is attempted, nothing changes. (3) if an attempt is made to read the data at an unused address, an undefined value will be read. if writing to the unused address is attempted, nothing changes.
87 m pd17068 10. general-purpose ports a general-purpose port outputs high, low, and floating signals to external circuits and reads high and low signals from the external circuits. 10.1 overview table 10-1 indicates the relationship between the ports and port registers. general-purpose ports are classified into three types: i/o ports, input ports, and output ports. i/o ports can be divided into two types: in a bit i/o port, each bit (each pin) can be set to input or output mode. in a group i/o port, the bits can set to input or output mode in units of four bits (four pins). table 10-1 relationship between ports (pins) and port registers (1/2) port no. symbol i/o pin data setting method port register (data memory) bank address bit symbol (reserved word) 36 p0a 3 37 p0a 2 38 p0a 1 39 p0a 0 32 p0b 3 33 p0b 2 34 p0b 1 35 p0b 0 48 p0c 3 49 p0c 2 50 p0c 1 51 p0c 0 57 p0d 3 58 p0d 2 59 p0d 1 60 p0d 0 port 0a port 0b port 0c port 0d bank0 remarks symbol b 3 p0a3 b 2 p0a2 b 1 p0a1 b 0 p0a0 p0b3 p0b2 p0b1 p0b0 p0c3 p0c2 p0c1 p0c0 p0d3 p0d2 p0d1 p0d0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 70h p0a 71h p0b 72h p0c 73h p0d i/o (bit i/o) i/o (bit i/o) output input
88 m pd17068 table 10-1 relationship between ports (pins) and port registers (2/2) port no. symbol i/o pin data setting method port register (data memory) bank address bit symbol (reserved word) 15 p1a 3 16 p1a 2 17 p1a 1 18 p1a 0 11 p1b 3 12 p1b 2 13 p1b 1 14 p1b 0 53 p1c 3 54 p1c 2 55 p1c 1 56 p1c 0 6 p1d 3 7 p1d 2 8 p1d 1 9 p1d 0 port 1a port 1b port 1c port 0d bank1 remarks symbol b 3 p1a3 b 2 p1a2 b 1 p1a1 b 0 p1a0 p1b3 p1b2 p1b1 p1b0 p1c3 p1c2 p1c1 p1c0 p1d3 p1d2 p1d1 p1d0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 70h p1a 71h p1b 72h p1c 73h p1d output i/o (bit i/o) i/o (group i/o) output 19 p2a 0 40 p2b 3 41 p2b 2 42 p2b 1 43 p2b 0 44 p2c 3 45 p2c 2 46 p2c 1 47 p2c 0 20 p2d 2 21 p2d 1 22 p2d 0 port 2a port 2b port 2c port 2d bank2 b 3 b 2 b 1 b 0 p2a0 p2b3 p2b2 p2b1 p2b0 p2c3 p2c2 p2c1 p2c0 p2d2 p2d1 p2d0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 70h p2a 71h p2b 72h p2c 6fh p2d output output i/o (bit i/o) output no relevant pins no relevant pins always set to 0 always set to 0
89 m pd17068 10.2 general-purpose i/o ports (p0a, p0b, p1b, p1c, p2d) 10.2.1 configurations of the i/o ports (1) to (5) below describe the configurations of the i/o ports: (1) p0a (p0a 3 , p0a 2 ), p0b (p0b 2 , p0b 0 ), p1b (p1b 2 , p1b 1 , p1b 0 ), p2d (p2d 2 , p2d 1 , p2d 0 ) v dd v dd res signal output latch 1 0 i/o switching flag write instruction port register (1 bit) read instruction
90 m pd17068 (2) p1c (p1c 3 , p1c 2 /adc 7 , p1c 1 /adc 6 , p1c 0 /adc 5 ) output latch 1 0 a/d converter channel select signal (active low) a/d converter v dd v dd port register (1 bit) i/o switching flag write instruction read instruction
91 m pd17068 (3) p0a (p0a 1 , p0a 0 ) v dd res signal output latch port register (1 bit) i/o switching flag read instruction write instruction (4) p0b 3 /hscnt v dd v dd output latch 0 1 port register (1 bit) i/o switching flag write instruction read instruction read instruction (the level is usually low. it is driven high only when a read instruction is executed.) horizontal synchronizing signal counter
92 m pd17068 (5) p1b 3 /tmin v dd v dd res signal basic timer (external clock) output latch 1 0 port register (1 bit) i/o switching flag write instruction read instruction 10.2.2 using the i/o port the i/o select register of control register p0a, p0b, p1b, p1c, or p2d sets the i/o port to input or output mode. p0a, p0b, p1b, and p2d are bit i/o ports, each bit of which (each pin) can be set to input or output mode. to set the output data, write the data to the corresponding port register. to read the input data, execute an instruction to read the data. section 10.2.3 describes the configurations of the i/o select registers of the ports. sections 10.2.4 and 10.2.5 describe the use of the i/o port as an input port and/or output port. section 10.2.6 provides notes on using the i/o port.
93 m pd17068 10.2.3 control registers of the i/o ports port 0a bit i/o select register, port 0b bit i/o select register, port 1b bit i/o select register, port 1c group i/o select register, and port 2d bit i/o select register set pins p0a, p0b, p1b, p1c, and p2d in input or output mode, respectively. (1) to (5) below describe the configurations and functions of the control registers: (1) port 0a bit i/o select register flag symbol b 3 b 2 b 1 b 0 address read/write port 0a bit i/o select register p 0 a b i o 3 p 0 a b i o 2 p 0 a b i o 1 p 0 a b i o 0 37h r/w 0 1 0 1 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 sets the port to input or output mode. sets pin p0a 0 to input mode. sets pin p0a 0 to output mode. sets the port to input or output mode. sets pin p0a 1 to input mode. sets pin p0a 1 to output mode. sets the port to input or output mode. sets pin p0a 2 to input mode. sets pin p0a 2 to output mode. sets the port to input or output mode. sets pin p0a 3 to input mode. sets pin p0a 3 to output mode. register
94 m pd17068 (2) port 0b bit i/o select register flag symbol b 3 b 2 b 1 b 0 address read/write port 0b bit i/o select register p 0 b b i o 3 p 0 b b i o 2 p 0 b b i o 1 p 0 b b i o 0 36h r/w 0 1 0 1 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 sets the port to input or output mode. sets pin p0b 0 to input mode. sets pin p0b 0 to output mode. sets the port to input or output mode. sets pin p0b 1 to input mode. sets pin p0b 1 to output mode. sets the port to input or output mode. sets pin p0b 2 to input mode. sets pin p0b 2 to output mode. sets the port to input or output mode. sets pin p0b 3 to input mode. sets pin p0b 3 to output mode. register
95 m pd17068 (3) port 1b bit i/o select register flag symbol b 3 b 2 b 1 b 0 address read/write port 1b bit i/o select register p 1 b b i o 3 p 1 b b i o 2 p 1 b b i o 1 p 1 b b i o 0 35h r/w 0 1 0 1 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 sets the port to input or output mode. sets pin p1b 0 to input mode. sets pin p1b 0 to output mode. sets the port to input or output mode. sets pin p1b 1 to input mode. sets pin p1b 1 to output mode. sets the port to input or output mode. sets pin p1b 2 to input mode. sets pin p1b 2 to output mode. sets the port to input or output mode. sets pin p1b 3 to input mode. sets pin p1b 3 to output mode. register
96 m pd17068 (4) port 1c group i/o select register flag symbol b 3 b 2 b 1 b 0 address read/write port 1c group i/o select register 000 p 1 c g i o 27h r/w 0 1 upon reset power-on clock stop ce 0000 0 0 sets the port to input or output mode. sets pins p1c 3 to p1c 0 to input mode. sets pins p1c 3 to p1c 0 to output mode. always set to 0. register
97 m pd17068 (5) port 2d bit i/o select register flag symbol b 3 b 2 b 1 b 0 port 2d bit i/o select register 0 p 2 d b i o 2 p 2 d b i o 1 p 2 d b i o 0 26h r/w 0 1 0 1 0 1 upon reset power-on clock stop ce 00 0 0 0 0 0 0 0 0 address read/write register sets the port to input or output mode. sets pin p2d 0 to input mode. sets pin p2d 0 to output mode. sets the port to input or output mode. sets pin p2d 1 to input mode. sets pin p2d 1 to output mode. sets the port to input or output mode. sets pin p2d 2 to input mode. sets pin p2d 2 to output mode. always set to 0.
98 m pd17068 10.2.4 using an i/o port as an input port select the pin to be set to input mode, using the i/o select register of each port. the pins of port 1c can be set to input mode only in units of four bits. the specified input pin enters the floating (hi-z) status and waits for the input of an external signal. to read the input data, execute a read instruction (such as skt) for the port register corresponding to the pin. if the signal input to the pin is high, 1 is read from the corresponding port register. if the input signal is low, 0 is read from the port register. if a write instruction (such as mov) is executed for the port register corresponding to an input port, the contents of the output latch are rewritten. 10.2.5 using an i/o port as an output port select the pin to be set to output mode, using the i/o select register of each port. the pins of port 1c can be set in the output mode only in units of four bits. the specified output pin outputs the contents of the output latch. to set the output data, execute a write instruction (such as mov) for the port register corresponding to the pin. to output a high signal to a pin, write 1. to output a low signal, write 0. to set a port to the floating state, set the port to input mode. if a read instruction (such as skt) is executed for the port register corresponding to an output port, the contents of the output latch are read. for the p0a 0 and p0a 1 pins, the status of the pin is read as is. the contents of the output latch and the read data may differ (see section 10.2.6 ). 10.2.6 notes on using the i/o port if the p0a 0 and p0a 1 pins are used for output as described below, the contents of the output latches may be rewritten. example setting the p0a 0 and p0a 1 pins as output ports initflg not p0abio3, not p0abio2, p0abio1, p0abio0 ; sets the p0a 1 and p0a 0 pins to output mode. initflg not p0a3, not p0a2, poa1, poa0 ; outputs a high signal to the p0a 1 and p0a 0 pins. ; # clr1 p0a1 ; outputs a low signal to the p0a 1 pin. macro expansion and . mf. p0a1 shr 4, #. df. (not p0a1 and 0fh) if the signal on pin p0a 0 is driven low by the execution of instruction # above, the clr1 instruction rewrites the contents of the output latch of pin p0a 0 to 0. if an instruction to read, the contents of port register p0a are executed when the p0a 0 or p0a 1 pin is set to output mode, the contents of the output latch are rewritten to the current signal level of the pin, even though the actual contents of the output latch are not changed.
99 m pd17068 10.2.7 statuses of the i/o ports upon reset (1) at power-on reset all pins are set to input mode. the contents of the output latches are set to 0. (2) at ce reset all pins are set to input mode. the contents of the output latches are retained. (3) at a clock-stop all pins are set to input mode. the contents of the output latches are retained. (4) in the halt state the previous statuses are retained. 10.3 general-purpose input port (p0d) 10.3.1 configuration of the input port the configuration of the input port is shown below: l p0d (p0d 3 to p0d 0 ) to the a/d converter v dd input latch port register (1 bit) write instruction read instruction read instruction 10.3.2 using the input port to read the input data, execute an instruction to read the contents of port register p0d (such as skt). if the signal input to a pin is high, 1 is read from the corresponding port register. if the input signal is low, 0 is read from the port register. if a write instruction (such as mov) is executed for a port register, nothing changes.
100 m pd17068 10.3.3 notes on using the input port p0d is internally pulled down if it is used as a general-purpose port. 10.3.4 statuses of the input port upon reset (1) at power-on reset all pins are set to input mode. (2) at ce reset all pins are set to input mode. (3) at a clock-stop all pins are set to input mode. they are internally pulled down. (4) in the halt state the previous statuses are retained. 10.4 general-purpose output ports (p0c, p1a, p1d, p2a, p2b, p2c) 10.4.1 configurations of the output ports the configurations of the output ports are shown in (1) and (2) below: (1) p0c (p0c 3 , p0c 2 , p0c 1 , p0c 0 ), p1d (p1d 3 , p1d 2 , p1d 1 , p1d 0 ) v dd output latch port register (1 bit) write instruction read instruction
101 m pd17068 (2) p1a (p1a 3 , p1a 2 , p1a 1 , p1a 0 ), p2a (p2a 0 ), p2b (p2b 3 , p2b 2 , p2b 1 , p2b 0 ), p2c (p2c 3 , p2c 2 , p2c 1 , p2c 0 ) output latch port register (1 bit) write instruction read instruction 10.4.2 using the output port the output port outputs the contents of the output latch from each pin. to set the output data, execute a write instruction (such as mov) for the port register corresponding to each pin. to output a high signal to a pin, write 1. to output a low signal, write 0. the pins of p1a, p2a, p2b, and p2c are n-ch open-drain output. the pins enter the floating status if a high signal is output. if a read instruction (such as skt) is executed for a port register, the contents of the output latch are read. 10.4.3 statuses of the output port upon reset (1) at power-on reset the contents of the output latch are output. the contents of the output latch are undefined. if required, initialize them by a program before setting a pin to output mode. (2) upon ce reset the contents of the output latch are output. the output latch retains the data existing immediately before the reset. if a pin is directly set to output mode, the previous contents are output. (3) upon a clock stop the contents of the output latch are output. the output latch retains the last data existing immediately before the reset. if a pin is directly set to output mode, the previous contents are output. (4) in the halt state the previous statuses are retained.
102 m pd17068 11. interrupt 11.1 outline of the interrupt block fig. 11.1 is an outline of the interrupt block. as shown in the figure, when an interrupt is requested by peripheral hardware, the interrupt block suspends the program currently being executed and causes a branch to a vector address. the interrupt block contains interrupt control blocks, provided for each item of peripheral hardware, and an interrupt enable flip-flop that enables all interrupts. the interrupt block also contains a stack pointer, an address stack register, a program counter, and an interrupt stack, all of which are controlled when an interrupt is accepted. the interrupt control block for each item of peripheral hardware consists of an interrupt request flag (irq ) that detects an interrupt request, an interrupt enable flag (ip ) that enables the interrupt, and a vector address generator (vag) that specifies a vector address when the interrupt is accepted. the following lists the peripheral hardware that supports the interrupt function: ? int 0 pin ? int nc pin ? timer 0 ? timer 1 ? basic timer 2 ? vram pointer ? interrupt group 0 (timer 0 overflow) ? interrupt group 1 (v sync or h sync signal) ? serial interface 0 ? serial interface 1
103 m pd17068 fig. 11-1 schematic diagram of interrupt block interrupt group 0 serial interface 1 serial interface 0 interrupt group 1 vram pointer basic timer 2 timer 1 timer 0 ipgrp0 flag irqgrp0 flag ipsio1 flag irqsio1 flag vector address generator 01h vector address generator 02h ipsio0 flag irqsio0 flag 1pgrp1 flag 1rqgrp1 flag ipidcvp flag irqidcvp flag ipbtm2 flag irqbtm2 flag iptm1 flag irqtm1 flag iptm0 flag irqtm0 flag ip0 flag irq0 flag ipnc flag irqnc flag vector address generator 03h vector address generator 04h vector address generator 05h vector address generator 06h vector address generator 07h vector address generator 08h vector address generator 09h vector address generator 0ah program counter stack pointer address stack register system register interrupt control block int 0 pin int nc pin di, ei instructions interrupt enable flip-flop interrupt stack
104 m pd17068 11.2 interrupt control blocks an interrupt control block is provided for each item of peripheral hardware. the block indicates whether an interrupt has been requested by the associated peripheral hardware, enables the interrupt, and generates a vector address when the interrupt is accepted. 11.2.1 formats and functions of interrupt request flags (irq ) when an interrupt request is received from an item of peripheral hardware, the corresponding interrupt request flag is set to 1. it is reset to 0 once the interrupt has been accepted. when 1 is written into an interrupt request flag, via the window register, the effect is the same as when the corresponding interrupt request is generated. when interrupts are not enabled, for example, the interrupt request state can be detected by reading these interrupt request flags. once an interrupt request flag has been set to 1, it is not reset until the corresponding interrupt request is accepted, or a 0 is written into the flag via the window register. when more than one interrupt request occurs at any one time, and one of these interrupt requests is accepted, the interrupt request flags for the other interrupt requests are not reset. the interrupt request flags are set in interrupt request registers in the register file. figs. 11-2 to 11-11 illustrate the formats and functions of the interrupt request registers. fig. 11-2 format of interrupt request register 1 flag symbol b 3 b 2 b 1 b 0 address read/write 3fh i n t n c 00 i r q n c 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 00 low level high level register interrupt request register 1 r/w r for bit 3 only sets the interrupt request state for the int nc pin. interrupt not requested interrupt requested fixed to 0 detects the input level on the int nc pin.
105 m pd17068 fig. 11-3 format of interrupt request register 2 fig. 11-4 format of interrupt request register 3 flag symbol b 3 b 2 b 1 b 0 i n t 0 00 i r q 0 3eh 0 1 0 1 upon reset power-on clock stop ce register address interrupt request register 2 r/w r for bit 3 only sets the interrupt request state for the int 0 pin. interrupt not requested interrupt requested fixed to 0 detects the input level on the int 0 pin. low level high level 0000 00 00 read/write flag symbol b 3 b 2 b 1 b 0 address read/write 000 i r q t m 0 3dh r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 upon reset register interrupt request register 3 sets the timer 0 interrupt request state. interrupt not requested interrupt requested fixed to 0
106 m pd17068 fig. 11-5 format of interrupt request register 4 flag symbol b 3 b 2 b 1 b 0 000 i r q t m 1 3ch r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 4 sets the timer 1 interrupt request state. interrupt not requested interrupt requested fixed to 0 fig. 11-6 format of interrupt request register 5 flag symbol b 3 b 2 b 1 b 0 000 i r q b t m 2 3bh r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 5 sets the basic timer 2 interrupt request state. interrupt not requested interrupt requested fixed to 0
107 m pd17068 fig. 11-7 format of interrupt request register 6 fig. 11-8 format of interrupt request register 7 flag symbol b 3 b 2 b 1 b 0 000 i r q i d c v p 3ah r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 6 sets the vram pointer interrupt request state. interrupt not requested interrupt requested fixed to 0 flag symbol b 3 b 2 b 1 b 0 i n t g r p 1 i r q g r p 1 0 0 2ch 0 1 0 1 power-on clock stop ce 0000 00 0 0 low level high level address read/write upon reset register interrupt request register 7 interrupt not requested interrupt requested r/w r for bit 3 only sets the interrupt group 1 interrupt request state. fixed to 0 detects the input level of the v sync or h sync signal.
108 m pd17068 fig. 11-9 format of interrupt request register 8 fig. 11-10 format of interrupt request register 9 flag symbol b 3 b 2 b 1 b 0 000 i r q s i o 0 2bh r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 8 interrupt not requested interrupt requested sets the serial interface 0 interrupt request state. fixed to 0 flag symbol b 3 b 2 b 1 b 0 000 i r q s i o 1 2ah r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 9 interrupt not requested interrupt requested sets the serial interface 1 interrupt request state. fixed to 0
109 m pd17068 fig. 11-11 format of interrupt request register 10 flag symbol b 3 b 2 b 1 b 0 000 i r q g r p 0 29h r/w 0 1 power-on clock stop ce 0 0 0 0 0 0 address read/write upon reset register interrupt request register 10 interrupt not requested interrupt requested sets the interrupt group 0 interrupt request state. fixed to 0
110 m pd17068 11.2.2 interrupt enable flags (ip ) the interrupt enable flags enable the interrupts requested from the corresponding peripheral hardware. an interrupt can be accepted only when all of the following conditions are satisfied: ? the interrupt is enabled by the setting of the corresponding interrupt enable flag. ? the corresponding interrupt request flag indicates that an interrupt request has occurred. ? the ei instruction (enabling all interrupts) has been executed. the interrupt enable flags are arranged in interrupt enable registers on the register file. figs. 11-12 to 11-14 show the formats and functions of the interrupt enable registers. fig. 11-12 format of interrupt enable register 1 flag symbol b 3 b 2 b 1 b 0 address read/write i p t m 1 i p t m 0 i p 0 i p n c 2fh r/w 0 1 0 1 0 1 0 1 power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 upon reset register interrupt enable register 1 disables interrupts. enables interrupts. specifies whether to enable interrupts for the int nc pin. disables interrupts. enables interrupts. specifies whether to enable interrupts for the int 0 pin. disables interrupts. enables interrupts. specifies whether to enable interrupts for timer 0. disables interrupts. enables interrupts. specifies whether to enable interrupts for timer 1.
111 m pd17068 fig. 11-13 format of interrupt enable register 2 flag symbol b 3 b 2 b 1 b 0 address read/write i p s i o 0 i p g r p 1 i p i d c v p i p b t m 2 2eh r/w 0 1 0 1 0 1 0 1 power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 0 0 upon reset register interrupt enable register 2 disables interrupts. enables interrupts. specifies whether to enable interrupts for basic timer 2. disables interrupts. enables interrupts. specifies whether to enable interrupts for the vram pointer. disables interrupts. enables interrupts. specifies whether to enable interrupts for interrupt group 1. disables interrupts. enables interrupts. specifies whether to enable interrupts for serial interface 0.
112 m pd17068 fig. 11-14 format of interrupt enable register 3 flag symbol b 3 b 2 b 1 b 0 address read/write 00 i p g r p 0 i p s i o 1 2dh r/w 0 1 0 1 power-on clock stop ce 0 0 0 0 0 0 0 0 upon reset register interrupt enable register 3 disables interrupts. enables interrupts. specifies whether to enable interrupts for serial interface 1. disables interrupts. enables interrupts. specifies whether to enable interrupts for interrupt group 0. fixed to 0 11.2.3 vector address generator (vag) when an interrupt requested from an item of peripheral hardware has been accepted, the vector address generator generates the branch address (vector address) of a program memory location for the accepted interrupt source. table 11-1 lists the vector addresses generated for different interrupt sources. table 11-1 vector addresses for different interrupt sources interrupt source vector address int nc pin 000ah int 0 pin 0009h timer 0 0008h timer 1 0007h basic timer 2 0006h vram pointer 0005h interrupt group 1 (v sync or h sync pin) 0004h serial interface 0 0003h serial interface 1 0002h interrupt group 0 (timer 0 overflow) 0001h
113 m pd17068 11.3 interrupt stack register 11.3.1 format and functions of the interrupt stack register fig. 11-15 shows the format of the interrupt stack register. when an interrupt is accepted, the contents of the following system registers are saved in the interrupt stack register: ? window register (wr) ? bank register (bank) ? general-purpose register pointer (rp) ? program status word (psword) when an interrupt is accepted, the contents of the above system registers are saved in the interrupt stack register. then, the contents of all system registers, except the window register, are reset to 0. up to two levels of the system register contents can be saved in the interrupt stack register. therefore, up to two levels of interrupt are possible. the contents of the system registers are restored from the interrupt stack register once the interrupt return instruction (reti instruction) has been executed. fig. 11-15 format of the interrupt stack register window stack (wrsk) bank stack (banksk) register pointer stack, high (rphsk) register pointer stack, low (rplsk) status stack (pswsk) bit b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0h 1h interrupt stack register (intsk) name remark C : bit not saved 11.3.2 interrupt stack operation fig. 11-16 illustrates the operation of the interrupt stack. if more than two interrupt levels are accepted, the data saved first is removed from the stack, and so must be saved by software.
114 m pd17068 fig. 11-16 interrupt stack operation (a) when the number of interrupt levels does not exceed 2 (b) when the number of interrupt levels exceeds 2 11.4 stack pointer, address stack register, and program counter the address stack register holds the return address to which control returns from an interrupt handling routine. the stack pointer specifies the address of the address stack register. when an interrupt is accepted, the value of the stack pointer is decremented by one, and the current value of the program counter is saved in the address stack register location specified by the stack pointer. when the interrupt return instruction (reti instruction) is executed after execution of the interrupt handling routine, the contents of the address stack register location, specified by the stack pointer, are restored to the program counter. the stack pointer is then incremented by one. see also chapter 3 . 11.5 interrupt enable flip-flop (inte) the interrupt enable flip-flop enables all interrupts. when this flip-flop is set, all interrupts are enabled. if the flip-flop is reset, all interrupts are disabled. the flip-flop is set and reset by using dedicated instructions: the ei instruction (for setting) and the di instruction (for resetting). the ei instruction causes the flip-flop to be set once the instruction immediately after the ei instruction has been executed. the di instruction resets the flip-flop upon execution of the di instruction. when an interrupt is accepted, the flip-flop is reset automatically. nothing occurs when a di instruction is executed while interrupts are disabled (di state), or when an ei instruction is executed while interrupts are enabled (ei state). when a power-on reset occurs, when a clock-stop instruction is executed, or when a ce reset occurs, the flip-flop is reset. ab a a when v dd on reti reti ab a c b d c e d d d d d not defined not defined not defined not defined not defined not defined not defined interrupt a interrupt b interrupt a interrupt b interrupt c interrupt d interrupt e reti reti
115 m pd17068 11.6 accepting interrupts 11.6.1 operation for accepting interrupts and priorities interrupts are accepted in the following sequence: (1) when an interrupt condition (for example, a high-to-low input signal transition occurs on the int 0 pin) is satisfied, the peripheral hardware outputs an interrupt request signal to the associated interrupt request block. (2) upon receiving of the interrupt request signal from the peripheral hardware, the interrupt request block sets its interrupt request flag (irq0 flag for the int 0 pin, for example) to 1. (3) if the corresponding interrupt enable flag (ip0 flag for the irq0 flag, for example) is set to 1 when the interrupt request flag has been set to 1, the interrupt request block outputs 1. (4) the signal output from the interrupt request block is anded with the output of the interrupt enable flip-flop, and the interrupt acceptance signal is output. the interrupt enable flip-flop is set to 1 with the ei instruction, and is reset to 0 with the di instruction. if 1 is output from an interrupt request block while the interrupt enable flip-flop is set to 1, an interrupt is accepted. when an interrupt is accepted, the output of the interrupt enable flip-flop is applied to each interrupt request block via an and circuit, as shown in fig. 11-1. the signal applied to the interrupt request block for the accepted interrupt resets the corresponding interrupt request flag to 0, and causes the vector address corresponding to the interrupt to be output. if an interrupt request block outputs 1 at this time, the interrupt acceptance signal is not transferred to the subsequent interrupt request blocks. when more than one interrupt request is generated at any one time, the interrupts are accepted according to the priorities shown below. if the interrupt enable flag for an interrupt source is not set to 1, the interrupt for that interrupt source is not accepted. therefore, an interrupt with a high hardware priority can be disabled by resetting the corresponding interrupt enable flag to 0. table 11-2 interrupt priorities interrupt source priority int nc pin 1 int 0 pin 2 timer 0 3 timer 1 4 basic timer 2 5 vram pointer 6 interrupt group 1 7 serial interface 0 8 serial interface 1 9 interrupt group 0 10
116 m pd17068 11.6.2 timing charts for accepting interrupts fig. 11-17 shows the timing charts for accepting interrupts. the timing charts in (1) of fig. 11-17 apply to the use of one interrupt. timing chart (a) in (1) shows how an interrupt is accepted when the interrupt request flag is set to 1. timing chart (b) in (1) shows how an interrupt is accepted when the interrupt enable flag is set to 1. in both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and interrupt enable flag have all been set to 1. if the last flag or flip-flop is set to 1 during the execution of movt dbf, the first instruction cycle of the @ar instruction, or an instruction that satisfies the skip conditions, the interrupt is accepted after the execution of movt dbf, the second cycle of the @ar instruction, or the skipped instruction (nop instruction). the interrupt enable flip-flop is set in the instruction cycle immediately after the ei instruction. this means that when the interrupt request flag is set during the execution cycle of the ei instruction, the instruction immediately after the ei instruction is executed, after which the interrupt is accepted. the timing charts in (2) of fig. 11-17 apply to the use of multiple interrupts. when multiple interrupts are used, and their interrupt enable flags are all set, they are accepted according to the hardware priorities. the hardware priorities, however, can be changed by programming the settings of the interrupt enable flags. the interrupt cycle shown in fig. 11-17 is applied to operations performed after an interrupt has been accepted; these operations include the resetting of the interrupt request flag, specification of a vector address, and saving of the program counter contents. this cycle requires 2 m s (when an 8-mhz crystal is used), which is equal to the time required for executing one instruction. for details, see section 11.7 .
117 m pd17068 fig. 11-17 timing charts for accepting interrupts (1/2) (1) when one interrupt type (example: low-to-high transition on the int 0 pin) is used (a) with no interrupt mask time set with interrupt enable flag (ip ) # when an interrupt is accepted while a normal instruction is being executed (the instruction is not a movt instruction or an instruction that satisfies the skip conditions) $ when an interrupt is accepted while a movt instruction or an instruction that satisfies the skip conditions is being executed (b) with an interrupt pending period set with the interrupt enable flag ei mov wr, #0001b poke intpm1, wr instruction inte int 0 pin irq0 flag ip0 flag normal instruction interrupt cycle 2 s interrupt enable period interrupt accepted interrupt handling routine 1 instruction cycle ei mov wr, #0001b poke intpm1, wr instruction inte int 0 pin irq0 flag ip0 flag interrupt cycle interrupt enable period interrupt accepted interrupt handling routine movt dbf, @ar skip instruction ei mov wr, #0001b poke intpm1, wr inte irq0 flag ip0 flag instruction int 0 pin interrupt cycle interrupt accepted interrupt handling routine interrupt pending period
118 m pd17068 fig. 11-17 timing charts for accepting interrupts (2/2) (2) when multiple interrupts (example: int 0 and int nc pins) are used (a) with hardware priority mov wr, #0011b poke intpm1, wr ei ei inte irq nc flag ip0 flag ipnc flag instruction interrupt cycle int nc pin int 0 pin irq 0 flag interrupt pending period int nc pin interrupt accepted int nc pin interrupt handling int 0 pin interrupt pending period int 0 pin interrupt accepted int 0 pin interrupt handling interrupt cycle (b) with software priority mov wr, #0010b poke intpm1, wr ei mov wr, #0011b poke intpm1, wr ei inte irq nc flag irq 0 flag ip nc flag ip 0 flag instruction interrupt cycle interrupt cycle interrupt pending period int 0 pin interrupt handling int nc pin interrupt pending period int nc pin int 0 pin int 0 pin interrupt accepted int nc pin interrupt accepted int nc pin interrupt handling
119 m pd17068 11.7 operation after an interrupt is accepted when an interrupt is accepted, the following operations are performed, automatically and in the order shown: (1) the interrupt enable flip-flop and the interrupt request flag for the accepted interrupt request are reset to 0. this indicates that the interrupt disable state is entered. (2) the value in the stack pointer is decremented by one. (3) the program counter contents are saved to the address stack register location specified by the stack pointer. the saved program counter contents indicate the program memory address subsequent to the address at which the interrupt was accepted. if the interrupt was accepted during the execution of a branch instruction, for example, the branch destination address is indicated in the program counter. if the interrupt was accepted during the execution of a subroutine call instruction, the called address is indicated. if the skip conditions are satisfied in a skip instruction, the next instruction is executed as an nop instruction, after which the interrupt is accepted. in this case, the program counter indicates the address subsequent to the skipped instruction. (4) the contents of the window register (wr), bank register (bank), general-purpose register pointer (rp), and program status word (psword) are saved to the interrupt stack. (5) the contents of the vector address generator for the accepted interrupt are transferred to the program counter to branch to the interrupt handling routine. for operations (1) to (5) above, a special one-instruction cycle (2 m s), that does not involve the execution of a normal instruction, is required. such an instruction cycle is called an interrupt cycle. this means that one instruction cycle (2 m s) is required to branch to the corresponding vector address after the interrupt has been accepted. 11.8 return from the interrupt handling routine to return control from the interrupt handling routine to the processing being performed when the interrupt was accepted, the interrupt return instruction (reti instruction) is used. when the reti instruction is executed, the following operations are performed, automatically and in the order shown: (1) the contents of the address stack register location, specified by the stack pointer, are restored to the program counter. (2) the interrupt stack contents are restored to the window register (wr), bank register (bank), general- purpose register pointer (rp), and program status word (psword). (3) the stack pointer value is incremented by one. operations (1) to (3) above are performed during the one instruction cycle (2 m s) in which the reti instruction is executed. the reti instruction differs from the ret and retsk instructions, which are subroutine return instructions, only in operation (2) above (system register restoration).
120 m pd17068 11.9 external interrupts (int 0 pin, int nc pin, v sync pin, h sync pin) 11.9.1 outline of external interrupts fig. 11-18 is an outline of the external interrupts. as shown in the figure, an external interrupt request occurs on a rising or falling edge of a signal applied to the int 0 pin, int nc pin, v sync pin, or h sync pin. whether the rising or falling edge is to be used for requesting interrupts can be programmed separately for each pin. the int nc pin can be used as a special input pin for remote control by selecting an appropriate pulse width for accepting an interrupt. each pin is a schmitt-triggered input. this can prevent malfunctions due to noise. pulse widths of less than 1 m s are ignored. as the interrupt source, either the v sync or h sync pin (interrupt group 1) can be specified with the igrp1sl flag. see section 11.10.7 . fig. 11-18 schematic diagram of external interrupts int 0 pin int0 flag schmitt-triggered ieg0 flag edge detection block edge detection block edge detection block interrupt control block irq0 flag irqnc flag irqgrp1 flag int nc pin intnc flag intncmd0 - intncmd2 flags iegnc flag schmitt-triggered schmitt-triggered schmitt-triggered v sync pin h sync pin selection circuit igrp1sl flag intgrp1 flag ieggrp1 flag remark int0 intnc detect pin states. intgrp1 ieg0 iegnc select the interrupt edge. ieggrp1 igrp1sl : selects the interrupt source for interrupt group 1. intncmd0 to intncmd2 : select the pulse width for accepting interrupts.
121 m pd17068 11.9.2 edge detection blocks the edge detection blocks detect the input signal edge (rising or falling edge) that causes an interrupt request to be generated for the int 0 pin, int nc pin, and v sync and h sync pins. each input signal edge is selected with the interrupt edge selection register. fig. 11-19 shows the format and functions of the interrupt edge selection register. fig. 11-19 format of the interrupt edge selection register flag symbol b 3 b 2 b 1 b 0 address read/write 0 i e g g r p 1 i e g 0 i e g n c 1fh r/w 0 1 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 register interrupt edge selection register specifies the input edge at which an interrupt request is generated. (int nc pin) rising edge falling edge specifies the input edge at which an interrupt request is generated. (int 0 pin) rising edge falling edge specifies the input edge at which an interrupt request is generated. (h sync or v sync pin: selected by the igrp1sl flag) rising edge falling edge fixed to 0 note that when the edge used for requesting interrupts is changed by changing the setting of the interrupt edge selection flag, an interrupt request signal may be issued immediately. suppose that the ieg0 flag is set to 1 (falling edge), and that a high is applied to the int 0 pin, as shown in table 11-3. here, note that if the ieg0 flag is reset to 0, the edge detection circuit assumes that a rising edge has been input, and generates an interrupt request.
122 m pd17068 table 11-3 interrupt requests generated by changing the ieg0, iegnc, and ieggrp1 flag settings change in interrupt edge pin state generation of interrupt request interrupt request flag state selection flag setting 1 ? 0 low not generated previous state is held. (falling edge) (rising edge) high generated set to 1. 0 ? 1 low generated set to 1. (rising edge) (falling edge) high not generated previous state is held. 11.9.3 interrupt control block the levels of the signals applied to the pins can be detected with the intnc, int0, and intgrp1 flags, respectively. these flags are set and reset regardless of the interrupts. when the interrupt function is not being used, these flags can be used as a 3-bit general-purpose input port. when interrupts are not enabled, these flags can be used as general-purpose ports that can detect a rising or falling edge by reading the interrupt request flags. in this case, the interrupt request flags are not reset automatically; they must be reset by the program. also see section 11.2.1 .
123 m pd17068 11.9.4 input pin for remote control (int nc ) the input pin for remote control (int nc pin) differs from normal external interrupt input pins in that the pulse width for accepting interrupts can be selected from among several width options. the pulse width is specified with the intnc mode select register. fig. 11-20 shows the format and functions of the intnc mode select register. fig. 11-20 format of the intnc mode select register flag symbol b 3 b 2 b 1 b 0 address read/write 0 i n t n c m d 2 i n t n c m d 1 i n t n c m d 0 15h r/w int nc mode selector register 000 001 010 011 100 200 s 400 s 2 ms 4 ms upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 0 0 register specifies the pulse width for accepting int nc pin interrupts. accepts interrupts on the pulse edge. other than above not to be set fixed to 0 11.10 internal interrupts the following seven internal interrupt types are provided. ? timer 0 ? timer 1 ? basic timer 2 ? vram pointer ? serial interface 0 ? serial interface 1 ? interrupt group 0 (timer 0 overflow)
124 m pd17068 11.10.1 timer 0 interrupt an interrupt request is generated at regular intervals. see chapter 12 for details. 11.10.2 timer 1 interrupt an interrupt request is generated at regular intervals. see chapter 12 for details. 11.10.3 basic timer 2 interrupt an interrupt request is generated at regular intervals. see chapter 12 for details. 11.10.4 vram pointer interrupt an interrupt request is generated at regular intervals. see chapter 16 for details. 11.10.5 serial interface 0 interrupt upon the completion of serial output or serial input, an interrupt request can be generated. see chapter 15 for details. 11.10.6 serial interface 1 interrupt an interrupt request can be generated on the rising edge of the eighth clock pulse, counting from the start of serial interface 1. see chapter 15 for details.
125 m pd17068 11.10.7 interrupts by interrupt group 0 and interrupt group selection register interrupt group 0 generates an interrupt request when timer 0 overflows. for details of the conditions governing the request of interrupts, see chapter 12. whether to use interrupts caused by the overflow of timer 0 is specified with the igrp0sl flag of the interrupt group selection register. in addition, the interrupt group selection register selects the interrupt source for interrupt group 1 (external interrupts). fig. 11-21 shows the format and functions of the interrupt group selection register. caution to use interrupts caused by the overflow of timer 0, both the interrupt enable flag (ipgrp0) and the igrp0sl flag of the interrupt group selection register must be set to 1. fig. 11-21 format of the interrupt group selection register flag symbol b 3 b 2 b 1 b 0 address read/write 00 i g r p 1 s l i g r p 0 s l 0fh r/w 0 1 0 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 register interrupt group selection register specifies whether to use timer 0 overflow interrupts (group 0). does not use interrupts. uses interrupts. selects the interrupt source (group 1). v sync signal h sync signal fixed to 0
126 m pd17068 12. timers the timers in the m pd17068 are used to manage the time required to execute programs. 12.1 overview fig. 12-1 shows the block diagrams of the timers. the m pd17068 contains the following six different timers. ? basic timer 0 ? basic timer 1 ? basic timer 2 ? timer 0 (modulo scheme) ? timer 1 (modulo scheme) ? clock timer basic timers 0 and 1 are realized by detecting the state of a flip-flops that is set at constant intervals, using software. basic timer 2 issues an interrupt request at constant intervals. timers 0 and 1 are modulo timers. they issue an interrupt request at constant intervals. the clock timer counts seconds, minutes, hours, and days. basic timer 0 is used also to detect a power failure. the clock pulses for the timers except the clock timer are generated by dividing the frequency of the system clock (8 mhz). the clock pulse for the clock timer is generated by dividing a frequency of 32 khz. fig. 12-1 overview of timers (1/2) (1) basic timer 0 (2) basic timer 1 (3) basic timer 2 8 mhz flip-flop clock selection block btm0cy flag clock selection block btm1cy flag external clock 8 mhz flip-flop 8 mhz external clock interrupt request clock selection block
127 m pd17068 32 khz frequency divider seconds counter minutes counter hours counter days counter reset control 8 mhz clock selection block start/stop 8-bit counter modulo register match detected interrupt request 8 mhz clock selection block start/stop 12-bit counter modulo register interrupt request match detected interrupt request fig. 12-1 overview of timers (2/2) (4) timer 0 (5) timer 1 (6) clock timer
128 m pd17068 12.2 basic timer 0 12.2.1 overview of basic timer 0 fig. 12-2 shows the block diagram of basic timer 0. basic timer 0 is realized by detecting the state of a flip-flop that is set at constant intervals, using the btm0cy flag (bit 0 at address rf:17h). the contents of the flip-flop correspond to the states of the btm0cy flag on a one-to-one basis. when the btm0cy flag is read-accessed for the first time after a power-on reset, it is read as 0. from then on, the flag is set to 1 at constant intervals. after the ce pin goes from a low level to a high level, a ce reset occurs simultaneously when the btm0cy flag is set next time. a power failure can therefore be detected by reading the btm0cy flag when a system reset (power-on or ce reset) occurs. see chapter 20 for power failure detection. fig. 12-2 block diagram of basic timer 0 btm0ck0 flag btm0ck1 flag 8 mhz selector flip-flop set/clear btm0cy flag frequency divider clock selection block remarks 1. btm0ck1 and btm0ck0 (bits 1 and 0 of the basic timer 0 clock select register, respectively; see fig. 12-3 ) specify the time interval at which the btm0cy flag is set. 2. btm0cy (bit 0 of the basic timer 0 carry flip-flop judge register; see fig. 12-4 ) reflects the state of the flip-flop. 12.2.2 clock selection block the clock selection block divides the frequency of the system clock (8 mhz) and specifies the time interval at which the btm0cy flag is set, using the basic timer 0 clock select register. fig. 12-3 shows the configuration and function of the basic timer 0 clock select register.
129 m pd17068 fig. 12-3 configuration of the basic timer 0 clock select register 12.2.3 flip-flop and btm0cy flag the flip-flop is set at constant intervals, and its state is detected using the btm0cy flag of the basic timer 0 carry flip-flop judge register. the btm0cy flag is reset to 0 by reading its contents into a window register using the peek instruction (read & reset). the btm0cy flag is 0 at a power-on reset. it becomes 1 at a ce reset. so, it can be used as a power failure detection flag. even when power is supplied, the btm0cy flag will not be set until a read instruction is executed. once a read instruction is executed, the flag is set at constant intervals. fig. 12-4 shows the configuration and function of the basic timer 0 carry flip-flop judge register. flag symbol b 3 b 2 b 1 b 0 address read/write 00 b t m 0 c k 1 b t m 0 c k 0 0ch r/w basic timer 0 clock select register 0 0 1 0 0 1 1 1 100 ms 5 ms 1 ms 1 ms upon reset power-on clock stop ce 0 0 0 0 0 0 specify the time interval at which the btm0cy flag is set. fixed to ? hold register
130 m pd17068 fig. 12-4 configuration of the basic timer 0 carry flip-flop judge register flag symbol b 3 b 2 b 1 b 0 address read/write basic timer 0 carry flip-flop judge register 000 b t m 0 c y 17h r & reset 0 1 upon reset power-on clock stop ce 0 1 1 0 0 0 detects the state of the flip-flop. the flip-flop is not set. the flip-flop is set. fixed to "0" register 12.2.4 example of using basic timer 0 a sample program follows. the following program performs process a at every one second. example clr2 btm0ck1, btm0ck0 ; specifies that the btm0cy flag be set at intervals of 100 ms. loop: skt1 btm0cy ; branches to next if btm0cy is 0. br next add m1, #1 ; adds 1 to m1. skge m1, #0ah ; performs process a if m1 is 10 or greater (1 second). br next mov m1, #0 process a next: process b ; performs process b and branches to loop. br loop
131 m pd17068 12.2.5 time interval error in basic timer 0 there are two types of errors in basic timer 0; one type is related to the time interval at which the btm0cy flag is detected, and the other type can occur when the time interval at which the btm0cy flag is set is changed. each type of error is described under (1) and (2). (1) error related to the detection time of the btm0cy flag the time interval at which the btm0cy flag is detected must be shorter than the time interval at which the btm0cy flag is set. (see section 12.2.6. ) in other words, assuming that the btm0cy flag is detected at intervals of t check and is set at intervals of t set (100, 5, or 1 ms), the relationship between t check and t set must be as follows: t check < t set under this condition, the time interval error encountered when the btm0cy flag is detected is as follows: 0 < error < t set fig. 12-5 basic timer 0 error related to the detection time of the btm0cy flag t set t check1 t check2 t check3 skt1 btm0cy # skt1 btm0cy $ skt1 btm0cy % skt1 btm0cy & btm0cy flag set pulse btm0cy flag h l 1 0 as shown in fig. 12-5, when the btm0cy flag is detected at $ , the timer is updated because the flag is 1. when the flag is detected at % , because it is 0, the timer is not updated until it is detected again at & . therefore, the timer is incremented by t check3 .
132 m pd17068 (2) error due to a change to the time interval at which the btm0cy flag is set the btm0ck1 and btm0ck0 flags specify the time interval at which the btm0cy flag is set. as shown in s ection 12.2.2 , the time interval set pulse can be selected from three types, 1 khz, 200 hz, and 10 hz. these three pulses operate independently. when the time interval set pulse is switched using the btm0ck1 and btm0ck0 flags, therefore, an error occurs as explained in the following example. example ; # initflg not btm0ck1, btm0ck0 ; selects 200 hz (5 ms) as the btm0cy flag set pulse. process a ; $ initflg btm0ck1, not btm0ck0 ; selects 1 khz (1 ms) as the btm0cy flag set pulse. process a ; % initflg not btm0ck1, btm0ck0 ; selects 200 hz (5 ms) as the btm0cy flag set pulse. with this coding, the btm0cy flag set pulse is switched as shown in fig. 12-6. fig. 12-6 btm0cy flag set pulse switching #$ % skt1 btm0cy h l h l h l 1 0 200 hz internal pulse 1 khz internal pulse btm0cy flag set pulse btm0cy flag as shown in fig. 12-6, when the btm0cy flag set time interval is switched, if the selected pulse falls, the btm0cy flag maintains its previous state ( $ in the figure). if the selected pulse rises, the btm0cy flag is set to 1 ( % in the figure). this example illustrates switching between 200 hz (5 ms) and 1 khz (1 ms). this explanation also applies to switching between 200 hz and 10 hz (100 ms) and between 1 khz and 10 hz.
133 m pd17068 consequently, if the btm0cy flag set time interval is switched as shown in fig. 12-7, a time interval error observed before the btm0cy flag is set for the first time is as given below. C t set < error < t check t set : newly selected btm0cy flag set time interval t check : btm0cy flag detection time interval the 10 hz, 200 hz, and 1 khz internal pulses have a phase difference from one another. these phase differences are shorter than the pulse interval and included in the error described above. see section 12.4.5 for each pulse phase difference. fig. 12-7 timer error that occurs when the btm0cy flag set time interval is switched from a to b t set skt1 btm0cy 0 t set 0 t check h l h l h l h l internal pulse a internal pulse b btm0cy flag set pulse btm0cy flag true timer interval actual timer interval time interval switched true timer interval actual timer interval time interval switched if the btm0cy flag is detected right after the timer interval is switched, the flag appears to be "1", resulting in an error of ? set . if the timer interval is switched right after the btm0cy flag is detected, the btm0cy flag is kept to be reset for one cycle, resulting in an error of t check .
134 m pd17068 12.2.6 cautions for using basic timer 0 (1) btm0cy flag detection time interval keep the btm0cy flag detection time interval shorter than the btm0cy flag set time interval. otherwise, the btm0cy flag cannot be set if the time required for process b is longer than the btm0cy flag set time interval, as shown in fig. 12-8. fig. 12-8 btm0cy flag and its detection h l 1 0 btm0cy flag set pulse btm0cy flag #$ % & ( skt1 btm0cy skt1 btm0cy skt1 btm0cy process a process b because the time required for process b is long after the btm0cy flag, which is set to "1" at $ , is detected, the btm0cy flag, which is set to "1" at % , cannot be detected. (2) sum of the timer update process time and the btm0cy flag detection time interval as explained in (1), the btm0cy flag detection time interval (t set ) must be kept shorter than the btm0cy flag set time interval. even when the btm0cy flag detection time interval is short, however, if the timer update process time is long, a ce reset may prevent a normal timer update process. the following conditions must therefore be satisfied. t check + t timer < t set where t check : btm0cy flag detection time interval t timer : timer update process time t set : btm0cy flag set time interval the coding that meets these conditions is given below.
135 m pd17068 example timer update process and btm0cy flag detection time interval start: clr2 btm0ck1, btm0ck0 ; specifies 100 ms as the btm0cy flag set time ; interval. btimer: ; # skt1 btm0cy ; updates the timer if the btm0cy flag is 1. br aaa timer update br btimer aaa: process a br btimer the timing chart for this coding is as follows: h l h l 1 0 # skt1 btm0cy # skt1 btm0cy ce pin btm0cy flag set pulse btm0cy flag btm0cy detection time interval timer update process ce reset a ce reset occurs if this timer update process takes long time. t chck t timer
136 m pd17068 (3) correcting the basic timer 0 carry at a ce reset the following paragraphs describe an example of correcting the timer at a ce reset. as explained in the example, it is necessary to correct the timer at a ce reset, if the btm0cy flag is used both to detect a power failure and to control the clock timer. the btm0cy flag is reset (0) when the supply voltage is first applied (at a power-on reset), and kept disabled from being set until it is read-accessed using the peek instruction. when the ce pin goes from a low level to a high level, a ce reset occurs in synchronization with the rising edge of the btm0cy flag set pulse, setting the btm0cy flag to 1 and making it active. detecting the state of the btm0cy flag at a system reset (power-on or ce reset) can therefore check for a power failure. if the flag is 0, it means that a power-on reset has occurred. if it is 1, it means that a ce reset has occurred (power failure detection). in this case, a clock timer must keep operating even at a ce reset. however, reading the btm0cy flag for power failure detection resets the flag (0) and makes it impossible to detect the set (1) state of the flag for one cycle. to solve this problem, it is necessary to update the clock timer if an attempt to detect a power failure detects a ce reset. see section 20.6 for power failure detection. example correcting the timer at a ce reset (when the btm0cy flag is used for both power failure detection and timer update) start : ; program address 0000h process a ; # skt1 btm0cy ; built-in macro ; checks the btm0cy flag and branches to initial br initial ; if the flag is 0 (power failure detected). backup : ; $ timer update by 100 ms ; timer correction because of backup (ce reset) loop: ; % process b ; while performing process b, skf1 btm0cy ;tests the btm0cy flag and updates the timer. br backup br loop initial : clr2 btm0ck1, btm0ck0 ; built-in macro ; the btm0cy flag set time interval is set to ; 100 ms and process c is performed because a ; power failure (power-on reset) has occurred. process c br loop fig. 12-9 shows the timing chart for the above program.
137 m pd17068 fig. 12-9 timing chart ac b b b bb bb bbb a bbb %% %%% %% %% # %% 5 v 0 v v dd h ce l h l h l 1 0 10 hz internal pulse btm0cy flag set pulse btm0cy flag program processing program instruction supply voltage applied start at address 0 on a power-on reset timer incre- mented timer incre- mented timer incremented timer incremented timer incremented btm0cy flag detected start at address 0 on a ce reset timer updated because the btm0cy flag has been detected to be set (1) point a point b point c point d point e #% as shown in fig. 12-9, when supply voltage v dd is applied, the 10 hz internal pulse rises to make the program start at address 0000h. when the btm0cy flag is detected at point a, the btm0cy flag appears to be reset (0) because it is just after power is supplied. consequently, it is determined that a power failure (power-on reset) has occurred. so, process c is performed to select 100 ms as the btm0cy flag set pulse. because the btm0cy flag is once read-accessed at point a, the btm0cy flag will be set (1) at intervals of 100 ms. even when the ce pin goes to a low at point b and goes to a high at point c, the program continues to update the clock while performing process b, unless the clock stop instruction is executed. because the ce pin goes from a low to a high at point c, a ce reset occurs at point d, where the btm0cy flag set pulse rises, to start the program at address 0000h. when the btm0cy flag is detected at point e, it is determined that a backup (ce reset) has occurred, because the flag appears to be set (1). also, as easily seen from the figure, if the clock is not updated by 100 ms at point e, the clock loses 100 ms every time a ce reset occurs. if process a takes more than 100 ms to detect for a power failure at point e, it is impossible to detect the btm0cy flag for two cycles. therefore, process a must be performed within 100 ms. the above description applies also when either 5 ms or 1 ms is selected as the btm0cy flag set pulse. it is necessary, therefore, to detect the btm0cy flag for power failure detection after the program starts at address 0000h and before the btm0cy flag is set.
138 m pd17068 h l h l 1 0 skt 1 btm0cy skt 1 btm0cy ce reset h l 1 0 skt1 btm0cy (peek ) (skt ) ce pin btm0cy flag set pulse btm0cy flag btm0cy flag set pulse btm0cy flag instruction built-in macro 2 s if the btm0cy flag is read during this period, a ce reset is deferred by one cycle. normally, the program starts at address 0000h at this point, but a ce reset does occur because the program to read the btm0cy flag also happens to run. peek wr,. mf. btm0cy shr 4 skt wr, #, df. btm0cy and 000fh (4) when the btm0cy flag is detected simultaneously with a ce reset as described in (3), a ce reset occurs at the same time the btm0cy flag is set (1). under this condition, if a read instruction is executed for the btm0cy flag simultaneously with a ce reset, the read instruction takes preference. therefore, if a btm0cy flag read instruction occurs simultaneously with the rising edge of the btm0cy flag set pulse that occurs after the ce pin goes from a low to a high, a ce reset occurs when the btm0cy flag is set on the next cycle. this operation is illustrated in fig. 12-10. fig. 12-10 operation that occurs if a ce reset occurs simultaneously with a btm0cy flag read instruction therefore, if a program is designed to detect the btm0cy flag cyclically and has the btm0cy flag detection time interval that matches the btm0cy flag set time interval, a ce reset may not occur for ever. observe the following cautions. because one instruction cycle is 2 m s (1/500 khz), the btm0cy flag is read at every 1 ms (2 m s 500) if the program is designed to detect the btm0cy flag once every 500 instructions. in this case, regardless of which of 1, 5, and 100 ms is selected as the timer interval set pulse, a ce reset will not occur for ever once the btm0cy flag set and detection time intervals coincide with each other. to solve this problem, do not create a program with a cycle that meets the following condition. (t set 500) = n (where n is a natural number) x t set : btm0cy flag set time interval x : number of steps in a cycle that a btm0cy flag read instruction is issued an example of a program that meets the above condition is given below. do not create such a program.
139 m pd17068 example process a set2 btm0ck1, btm0ck0 ; built-in macro ; specifies 1 ms as the btm0cy flag set pulse. loop : ; # skt1 btm0cy ; built-in macro br bbb aaa : 496 steps br loop bbb : 496 steps br loop in this example, a ce reset will not occur for ever if the btm0cy flag happens to be set at a timing of a btm0cy flag read instruction at # , because the read instruction is repeated at every 500 instructions.
140 m pd17068 12.3 basic timer 1 12.3.1 overview of basic timer 1 fig. 12-11 shows the block diagram of basic timer 1. basic timer 1 is realized by detecting the state of a flip-flop that is set at constant intervals, using the btm1cy flag (bit 0 at address rf:16h). the contents of the flip-flop corresponds the states of the btm1cy flag on a one-to-one basis. basic timer 1 can use an external clock input at the p1b 3 /tmin pin as its base clock. it can also detect the zero cross of the external clock. fig. 12-11 block diagram of basic timer 1 btm1zx flag 8 mhz p1b 3 /tmin (external clock) btm1exck flag btm1ck1 flag btm1ck0 flag selector flip- flop set/clear btm1cy flag zero-cross detection circuit frequency divider clock selection block remarks 1. btm1exck (bit 3 of basic timer 1 mode select register; see fig. 12-12 ) specifies the base clock (internal or external clock). 2. btm1zx (bit 2 of basic timer 1 mode select register; see fig. 12-12 ) specifies whether the zero- cross detection circuit is on or off. 3. btm1ck1 and btm1ck0 (bits 1 and 0 of the basic timer 1 mode select register, respectively; see fig. 12-12 ) specify the time interval at which the btm1cy flag is set. 4. btm1cy (bit 0 of the basic timer 1 carry flip-flop judge register; see fig. 12-13 ) reflects the state of the flip-flop.
141 m pd17068 12.3.2 clock selection block the clock selection block divides the frequency of the system clock (8 mhz) or an external clock and specifies the time interval at which the btm1cy flag is set, using the basic timer 1 mode select register. either the system clock (8 mhz) or an external clock input at the p1b 3 /tmin pin can be selected as the base clock of basic timer 1. when an external clock is selected, it is possible to select whether the zero-cross detection circuit is turned on or off. fig. 12-12 shows the configuration and function of the basic timer 1 mode select register. fig. 12-12 configuration of the basic timer 1 mode select register flag symbol b 3 b 2 b 1 b 0 address read/write basic timer 1 mode select register 0bh r/w b t m 1 e x c k b t m 1 z x b t m 1 c k 1 b t m 1 c k 0 0 00 0 01 0 10 0 11 10 0 11 0 10 1 11 1 upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 specify the time interval at which the btm1cy flag is set and whether the zero- cross detection circuit is turned on or off. 100 ms 5 ms 1 ms 125 s divides the frequency of an external clock (at the p1b 3 /tmin pin) by 5. divides the frequency of an external clock (at the p1b 3 /tmin pin) by 6. divides the frequency of an external clock (at the p1b 3 /tmin pin) by 5 (with the zero-cross detection circuit on). divides the frequency of an external clock (at the p1b 3 /tmin pin) by 6 (with the zero-cross detection circuit on). hold register remark : dont care
142 m pd17068 12.3.3 flip-flop and btm1cy flag the flip-flop is set at constant intervals, and its state is detected using the btm1cy flag of the basic timer 1 carry flip-flop judge register. the btm1cy flag is reset to 0 by reading its contents into a window register using the peek instruction (read & reset). even when power is supplied, the btm1cy flag will not be set until a read instruction is executed. once a read instruction is executed, the flag is set at constant intervals. fig. 12-13 shows the configuration and function of the basic timer 1 carry flip-flop judge register. fig. 12-13 configuration of the basic timer 1 carry flip-flop judge register upon reset power-on clock stop ce 0 1 0 0 0 1 flag symbol b 3 b 2 b 1 b 0 address read/write basic timer 1 carry flip-flop judge register 000 b t m 1 c y 16h r & reset 0 1 detects the state of the flip-flop. the flip-flop is not set. the flip-flop is set. fixed to "0" register 12.3.4 time interval error in basic timer 1 similarly to basic timer 0, there are two types of errors in basic timer 1; one type is related to the detection time interval of the btm1cy flag, and the other type can occur when the time interval at which the btm1cy flag is set is changed. see section 12.2.5.
143 m pd17068 12.4 basic timer 2 12.4.1 overview of basic timer 2 fig. 12-14 shows the block diagram of basic timer 2. basic timer 2 issues interrupt requests at constant intervals and sets (1) the irqbtm2 flag. if an ei instruction has been executed and the ipbtm2 flag has been set, the basic timer 2 interrupt requests are accepted when the irqbtm2 flag is set. (see chapter 11. ) basic timer 2 can use an external clock input at the p1b 3 /tmin pin as its base clock. it can also detect the zero cross of the external clock. fig. 12-14 block diagram of basic timer 2 p1b 3 /tmin (external clock) btm2zx flag 8 mhz btm2exck flag btm2ck1 flag btm2ck0 flag selector clock selection block frequency divider irqbtm2 set signal zero-cross detection circuit remarks 1. btm2exck (bit 3 of the basic timer 2 mode select register; see fig. 12-15 ) specifies the base clock (internal or external clock). 2. btm2zx (bit 2 of the basic timer 2 mode select register; see fig. 12-15 ) specifies whether the zero-cross detection circuit is on or off. 3. btm2ck1 and btm2ck0 (bits 1 and 0 of the basic timer 2 mode select register, respectively; see fig. 12-15 ) specify the time interval at which the irqbtm2 flag is set.
144 m pd17068 12.4.2 clock selection block the clock selection block divides the frequency of the system clock (8 mhz) or an external clock and specifies the time interval at which the irqbtm2 flag is set, using the basic timer 2 mode select register. either the system clock (8 mhz) or an external clock input at the p1b 3 /tmin pin can be selected as the base clock of basic timer 2. when an external clock is selected, it is possible to select whether the zero-cross detection circuit is turned on or off. with an external clock (8 mhz), it is also possible to select that the zero-cross detection circuits is on or off. fig. 12-15 shows the configuration and function of the basic timer 2 mode select register. fig. 12-15 configuration of the basic timer 2 mode select register flag symbol b 3 b 2 b 1 b 0 address read/write basic timer 2 mode select register b t m 2 e x c k b t m 2 z k b t m 2 c k 1 b t m 2 c k 2 0ah r/w upon reset power-on clock stop ce 0 0 0 0 0 0 0 0 100 ms 0 0 5 ms 0 0 1 ms 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 specify the time interval at which the irqbtm2 flag is set and whether the zero- cross detection circuit is turned on or off. 125 s divides the frequency of an external clock (at the p1b 3 /tmin pin) by 5. divides the frequency of an external clock (at the p1b 3 /tmin pin) by 6. divides the frequency of an external clock (at the p1b 3 /tmin pin) by 5 (with the zero-cross detection circuit on). divides the frequency of an external clock (at the p1b 3 /tmin pin) by 6 (with the zero-cross detection circuit on). hold register 0 1 0 remark : dont care
145 m pd17068 12.4.3 example of using basic timer 2 a sample program follows. example br aaa ; branches to aaa. btimer: ; program address 0006h add m1, #0001b ; adds 1 to m1. skt1 cy ; tests the cy flag. br bbb ; returns to the main routine if there is no carry. process a bbb: ei reti aaa: initflg not btm2exck, not btm2zx, btm2ck1, not btm2ck0 ; selects 1 ms as the basic timer 2 interrupt pulse. mov m1, #000b ; clears the m1 contents to 0. set1 ipbtm2 ; enables the basic timer 2 interrupt. ei ; enables all interrupts. loop: process b br loop the above program performs process a at intervals of 1 ms. note that when an interrupt request is accepted, subsequent interrupts are disabled. also note that even if interrupts are disabled, the irqbtm2 flag can be set to 1. in other words, if process a takes 1 ms or more, an interrupt request is accepted when a return is made by a reti instruction, thus disabling process b from being performed. 12.4.4 time interval error in basic timer 2 as explained in section 12.4.3 , if an ei instruction has been executed and basic timer 2 interrupts are enabled, an interrupt request is accepted each time the basic timer interrupt pulse rises. therefore, a basic timer 2 error occurs only when: (1) an interrupt request is accepted for the first time after basic timer 2 interrupts are enabled. (2) an interrupt request is accepted for the first time after a time interval at which the irqbtm2 flag is set is changed, that is after an interrupt pulse is changed, or (3) the irqbtm2 is write-accessed. fig. 12-16 shows the timing charts for errors that occur under the above conditions.
146 m pd17068 fig. 12-16 basic time 2 error (1/2) (a) when basic timer 2 interrupts are enabled t set ei ei # % $ h l 1 0 1 0 ei di irqbtm2 flag irqbtm2 flag inte flip-flop basic timer 2 interrupt pulse interrupt pending set1 ipbtm2 interrupt accepted interrupt accepted interrupt accepted when the ipbtm2 flag is set at point # in the above chart to enable basic timer 2 interrupts, an interrupt request is accepted immediately. a basic timer 2 error for this case is as follows: 0 (error) t set when an ei instruction is issued at point $ to enable interrupts, an interrupt occurs at point % , where the basic timer 2 interrupt pulse rises. a basic timer 2 error for this case is as follows: 0 (error) t set
147 m pd17068 fig. 12-16 basic time 2 error (2/2) (b) when the basic timer 2 interrupt pulse is switched h l h l h l 1 0 1 0 ei di irqbtm2 flag ipbtm2 flag inte flip-flop ei # $ % ei ei basic timer 2 interrupt internal pulse a basic timer 2 interrupt internal pulse b basic timer 2 interrupt pulse interrupt accepted interrupt accepted interrupt accepted basic timer 2 interrupt pulse switched basic timer 2 interrupt pulse switched ei even when the basic timer 2 interrupt pulse is switched from a to b at point # in the above chart, an interrupt request is not accepted at point $ because the basic timer 2 interrupt pulse does not rise. when the basic timer 2 interrupt pulse is switched from b to a at point % , an interrupt request is accepted immediately, because the basic timer 2 interrupt pulse rises. (c) when the irqbtm2 flag is manipulated h l 1 0 1 0 ei di ei ei # $ irqbtm2 flag ipbtm2 flag inte flip-flop basic timer 2 interrupt pulse interrupt accepted set1 irqbtm2 interrupt accepted clr1 irqbtm2 interrupt not accepted interrupt accepted when the irqbtm2 flag is set to 1 at point # in the above chart, an interrupt request is accepted immediately. if the irqbtm2 flag is reset to 0 at point $ at the same time the basic timer 2 interrupt pulse rises, an interrupt is not accepted.
148 m pd17068 12.4.5 cautions for using basic timer 2 when basic timer 2 is used in a program that runs at constant intervals once power is supplied (after power- on reset), such as a clock program, the program must complete interrupt handling related to basic timer 2 within a certain period of time. this is explained below, using an example. example m1 mem 0.10h ; 1 ms counter timer dat 0006h ; interrupt vector address symbol definition br start ; branches to start. org timer ; program address (0006h) add m1, #1010b ; add 1010b to the m1 contents. skt1 cy ; clock processing if a carry occurs br ei_reti ; makes a return if there is no carry. ; # clock processing ei_reti : ei reti start : clr2 btm0ck1, btm0ck0 ; built-in macro ; specifies that the btm0cy flag is set at ; intervals of 100 ms. clr4 btm2exck, btm2zx, btm2ck1, btm2ck0 ; built-in macro ; set the basic timer 2 interrupt time to ; 100 ms. set1 ipbtm2 ; enables basic timer 2 interrupts. ei ; enables all interrupts. loop: process a br loop in the above example, the clock processing is repeated at intervals of 1 second, while process a is performed. as shown in fig. 12-17 (a), when the ce pin goes from a low to a high, a ce reset occurs at the same time the btm0cy flag set pulse rises. if a basic timer 2 interrupt is requested at the same time the btm0cy flag is set, a ce reset takes preference. when a ce reset occurs, it automatically resets a basic timer 2 interrupt request (irqbtm2), hence failing to perform timer processing for one cycle.
149 m pd17068 h l h l h l ce pin btm0cy flag set pulse gap in time (550 s in this case) basic timer 2 interrupt pulse basic timer 2 interrupt basic timer 2 interrupt ce reset because there is a time gap of 550 s between when the basic timer 2 interrupt pulse rises and when the btm0cy flag set pulse rises, a ce reset will not hamper a normal timer process provided that the basic timer 2 interrupt handling is completed within 550 s. to solve this problem, as shown in fig. 12-17 (b), a gap in time is provided between when the btm0cy flag set pulse rises and when the basic timer 2 interrupt pulse rises. in this example, the clock processing is completed with 550 m s in order to eliminate a possibility that the occurrence of a ce reset prohibits acceptance of a basic timer 2 interrupt request. in other words, you should complete your basic timer 2 interrupt handling within 550 m s, if you want to enable basic timer 2 interrupts even at a ce reset. if 125 m s has been selected as the basic timer 2 interrupt time interval, however, the interrupt handling must be completed within 75 m s. a gap in time is also provided between the btm0cy flag set pulse and the btm1cy flag set pulse. fig. 12-17 timing chart (a) (b) h l l h l h ce pin btm0cy flag set pulse basic timer 2 interrupt pulse basic timer 2 interrupt a ce reset occurs at this point, thus failing to accept a basic timer 2 interrupt for one cycle, because the btm0cy flag set pulse rises.
150 m pd17068 12.5 timer 0 12.5.1 overview of timer 0 fig. 12-18 shows the block diagram of timer 0. timer 0 is realized by dividing the frequency of the basic clock (100 khz or 20 khz) using the 12-bit counter and by comparing the count in the 12-bit counter with a previously set value. fig. 12-18 block diagram of timer 0 remarks 1. tm0ck (bit 0 of timer 0 clock select register; see fig. 12-19 ) specifies the basic clock frequency. 2. tm0en (bit 0 of timer 0 control register; see fig. 12-20 ) specifies whether to start or stop timer 0. 3. tm0res (bit 1 of timer 0 control register; see fig. 12-20 ) specifies whether to reset the timer 0 counter. 4. tm0rpt (bit 2 of timer 0 control register; see fig. 12-20 ) selects the modulo count mode or free-run count mode. 5. tm0ovf (bit 0 of timer 0 overflow register; see fig. 12-21 ) detects when the timer 0 counter overflows. tm0ovf flag count block clock selection block tm0ck flag tm0res flag tm0rpt flag tm0en flag set/clear frequency divider selector timer 0 counter (tm0c) overflow irqgrp0 set signal match detection circuit match irqtm0 set signal timer 0 modulo register (tm0m) 12 dbf 12 dbf 8 mhz
151 m pd17068 register flag symbol address timer 0 clock select register specifies the basic clock for timer 0. fixed to "0" upon reset power-on clock stop hold read/write 000 t m 0 c k 09h r/w 100 khz (10 s) 20 khz (50 s) 0 0 ce 0000 0 b 3 b 2 b 1 b 0 12.5.2 clock selection block the clock selection block specifies the basic clock pulse used to run the timer 0 counter. two types of pulses can be selected as the basic clock pulse using the tm0ck flag. fig. 12-19 shows the configuration and function of the timer 0 clock select register. fig. 12-19 configuration of the timer 0 clock select register
152 m pd17068 12.5.3 count block the count block counts the basic clock pulses using the 12-bit timer 0 counter, and outputs the count. it also issues an interrupt request if the count matches the value in the timer 0 modulo register. the tm0en flag specifies whether to start or stop the basic clock pulse supplied to the timer 0 counter. the tm0res flag can reset the timer 0 counter. the timer 0 counter is not automatically reset when its content matches the value in the timer modulo register. the tm0rpt flag selects the modulo count or free-run count mode. in the free-run count mode, when the content of the timer 0 counter matches the content of the timer modulo register, timer 0 counter continues to be incremented without being reset. in the module count mode, when the content of the timer 0 counter matches the content of the timer modulo register, timer 0 counter continues to be incremented after reset. the tm0ovf flag can be used to detect when the counter overflows. it issues an interrupt request when an overflow occurs. the timer 0 counter can be read- and write-accessed through the data buffer. fig. 12-20 shows the configuration and function of the timer 0 control register. fig. 12-21 shows the configuration and function of the timer 0 overflow register. figs. 12-22 and 12-23 show the configuration of the timer 0 counter and timer 0 modulo register, respectively. fig. 12-20 configuration of the timer 0 control register register flag symbol address timer 0 control register r/w (for bit 0, w only) specifies whether to start or stop timer 0. stop. start. resets the timer 0 counter. do not reset. reset. selects a timer 0 mode. free-run count mode modulo count mode fixed to "0" upon reset power-on clock stop hold read/write b 3 b 2 b 1 b 0 0 t m 0 r p t t m 0 r e s t m 0 e n 0dh 0 1 0 1 0 1 ce 0000 000
153 m pd17068 fig. 12-21 configuration of the timer 0 overflow register register flag symbol timer 0 overflow register detects when the timer 0 counter overflows. no overflow overflow fixed to "0" upon reset power-on clock stop hold address read/write b 3 b 2 b 1 b 0 000 t m 0 o v f 0eh r 0 1 ce 0000 0 fig. 12-22 configuration of the timer 0 counter data buffer peripheral register register symbol peripheral address timer 0 counter count in the timer 0 counter fixed to "0" transfer data effective data dbf3 dbf2 dbf1 dbf0 16 get b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 m s b l s b tm0c 47h 0 x 2 12 - 1 (fffh) free-run count mode the counter goes up to fffh, then stops on the next clock pulse. modulo count mode the counter goes up to the value set in the timer 0 modulo register, then is reset back to 000h on the next clock and continues counting.
154 m pd17068 fig. 12-23 configuration of the timer 0 modulo register data buffer peripheral register register symbol peripheral address timer 0 modulo register value set in the timer 0 modulo register must not be set. modulo data fixed to "0" transfer data b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 l s b effective data m s b tm0m 46h get put 0 1 x 2 12 - 1 (fffh) 16 dbf3 dbf2 dbf1 dbf0
155 m pd17068 12.5.4 example of using timer 0 example 1. module count mode br start org 0004h tmint: process a ei reti start: clr1 tmck0 ;specifies 10 m s as the count clock. mov dbf2, #50 shr 8 and 0fh mov dbf1, #50 shr 4 and 0fh mov dbf0, #50 and 0fh put tm0m, dbf set1 iptm0 ei set3 tm0rpt, tm0res, tm0en loop: main process br loop this program performs process a at intervals of 500 m s. process a must be completed within 500 m s.
156 m pd17068 example 2. free-run count mode br start . . . start: clr1 tmck0 ;specifies 10 m s as the count clock. clr1 tm0rpt set2 tm0res, tm0en process a skf1 tm0ovf br overflow detected get dbf, tm0c . . . overflow detected: . . . this program measures the time required to perform process a. it can measure a period of time ranging from 10 m s to 40950 m s. (this program cannot measure a period longer than 40950 m s. a branch should be made to another routine.) the above sample program can be used to measure the pulse width of a remote control signal. the modulo count mode is convenient in issuing interrupt requests at constant intervals, while the free- run count mode is useful to measure total time. 12.5.5 time interval error in timer 0 timer 0 encounters up to one basic pulses worth of time interval error under the following conditions. (1) when the tm0en flag is manipulated when the tm0en flag is set, 0 to +1 pulses worth of error occurs. when the tm0en flag is reset, 0 to C1 pulses worth of error occurs. (2) when the counter is reset during operation when the counter is reset, 0 to +1 pulses worth of error occurs. (3) when the basic clock is switched during operation of the counter 0 to +1 newly selected pulses worth of error occurs. 12.5.6 cautions for using timer 0 a timer 0 interrupt request may occur simultaneously with other timer interrupt requests or a ce reset. if it is necessary to update the timer even at a ce reset, do not use timer 0. use basic timer 0, instead.
157 m pd17068 12.6 timer 1 12.6.1 overview of timer 1 fig. 12-24 shows the block diagram of timer 1. timer 1 is realized by dividing the frequency of the basic clock (100 khz, 10 khz, 20 khz, or 1 khz) using the 8-bit counter and by comparing the count in the 8-bit counter with a previously set value. fig. 12-24 block diagram of timer 1 remarks 1. tm1ck1 and tm1ck0 (bits 1 and 0 of timer 1 clock select register; fig. 12-25 ) specify the basic clock frequency. 2. tm1en (bit 0 of timer 1 control register; fig. 12-26 ) specifies whether to start or stop timer 1. 3. tm1res (bit 1 of timer 1 control register; fig. 12-26 ) specifies whether to reset the timer 1 counter. clock selection block count block tm1ck1 flag tm1ck0 flag tm1res flag tm1en flag frequency divider selector timer 1 counter (tm1c) match detection circuit match irqtm1 set signal timer 1 modulo register (tm1m) 8 dbf dbf 8 8 mhz
158 m pd17068 12.6.2 clock selection block the clock selection block specifies the basic clock pulse used to run the timer 1 counter. four types of pulses can be selected as the basic clock pulse using the tm1ck0 and tm1ck1 flags. fig. 12-25 shows the configuration and function of the timer 1 clock select register. fig. 12-25 configuration of the timer 0 clock select register register flag symbol timer 1 clock select register specifies the basic clock for timer 1. fixed to "0" upon reset power-on clock stop hold address read/write 1 khz 10 khz 20 khz 100 khz (1 ms) (100 s) (50 s) (10 s) 00 01 10 11 ce 0000 00 b 3 b 2 b 1 b 0 00 t m 1 c k 1 t m 1 c k 0 1ah r/w
159 m pd17068 12.6.3 count block the count block counts the basic clock pulses using the 8-bit timer 1 counter, and outputs the count. it also issues an interrupt request if the count matches the value in the timer 1 modulo register. the tm1en flag can start or stop the basic clock pulse supplied to the timer 1 counter. the tm1res flag can reset the timer 1 counter. the timer 1 counter is not automatically reset when its content matches the value in the timer 1 modulo register. the timer 1 counter can be read- and write-accessed through the data buffer. fig. 12-26 shows the configuration and function of the timer 1 control register. figs. 12-27 and 12-28 show the configuration and function of the timer 1 counter and timer 1 modulo register, respectively. fig. 12-26 configuration of the timer 1 control register register flag symbol timer 1 control register specifies whether to start or stop timer 1. stop. start. specifies whether to reset timer 1 counter. note do not reset. reset. fixed to "0" upon reset power-on clock stop hold address read/write b 3 b 2 b 1 b 0 00 t m 1 r e s t m 1 e n 1bh r/w 0 1 0 1 ce 0000 00 note this is effective only at write access. 0 is always read out.
160 m pd17068 fig. 12-27 configuration of the timer 1 counter fig. 12-28 configuration of the timer 1 modulo register data buffer peripheral register register symbol peripheral address timer 1 counter reads the count in the timer 1 counter. count transfer data effective data dbf3 dbf2 dbf1 dbf0 8 get b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 tm1c 06h x 0 0ffh hold hold data buffer peripheral register register symbol peripheral address timer 1 modulo register specify the data for the timer 1 modulo register. must not be set. modulo data effective data transfer data dbf3 dbf2 dbf1 dbf0 don't care don't care 8 get put b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 x 0ffh tm1m 05h
161 m pd17068 12.6.4 time interval error in timer 1 timer 1 encounters up to one basic pulses worth of time interval error under the following conditions. (1) when the tm1en flag is manipulated when the tm1en flag is set, 0 to +1 pulses worth of error occurs. when the tm1en flag is reset, 0 to -1 pulses worth of error occurs. (2) when the counter is reset during operation when the counter is reset, 0 to +1 pulses worth of error occurs. (3) when the basic clock is switched during operation of the counter 0 to +1 newly selected pulses worth of error occurs. 12.6.5 cautions for using timer 1 a timer 1 interrupt request may occur simultaneously with other timer interrupt requests or a ce reset. if it is necessary to update the timer even at a ce reset, do not use timer 1. use basic timer 0, instead.
162 m pd17068 12.7 clock timer 12.7.1 overview of the clock timer fig. 12-29 shows the block diagram of the clock timer. the clock timer is realized by counting seconds, minutes, hours, and days using a clock pulse and by reading out the counts. the clock pulse is generated by dividing a frequency of 32 khz. the clock timer can also be used as an ordinary timer by detecting a flip-flop that is set at 128 or 8 hz by software. fig. 12-29 block diagram of the clock timer clock frequency divider block count block wtmhld flag wtm 128hz flag wtm 8hz flag xtsel flag 128 hz carry flip-flop 8 hz carry flip-flop 32 khz oscillator frequency divider ckosel flag to port 1b seconds set register (wtmsec) minutes set register (wtmmin) hours set register (wtmhr) days set register (wtmday) seconds counter minutes counter hours counter days counter counter reset reset control wtmres0 to wtmres3 flags reset control block dbf p1b 1 /ckout 1 0 remarks 1. xtsel (bit 0 of the clock timer mode register; see fig. 12-32 ) selects the function of the p0d 0 / adc 1 /xt out and p0d 1 /adc 2 /xt in pins. 2. ckosel (bit 1 of the clock timer mode register; see fig. 12-32 ) specifies whether to output the clock timer adjustment oscillator. 3. wtm128hz (bit 0 of the clock timer 128 hz carry register; see fig. 12-30 ) detects the state of the 128 hz carry flip-flop. 4. wtm8hz (bit 0 of the clock timer 8 hz carry register; see fig. 12-31 ) detects the state of the 8 hz carry flip-flop. 5. wtmhld (bit 3 of the clock timer mode register; see fig. 12-32 ) specifies whether to hold the clock timer. 6. wtmres0 to wtmres3 (bits 0 to 3 of the clock timer reset register; see fig. 12-36 ) specifies whether to reset the clock timer.
163 m pd17068 12.7.2 clock frequency divider block the clock frequency block divides a frequency of 32 khz to generate a clock pulse used for the clock timer. the clock frequency block can also detect the wtm128hz flag (bit 0 of the clock timer 128 hz carry register) and the wtm8hz flag (bit 0 of the clock timer 8 hz carry register). setting (1) the wtmhld flag of the clock timer mode register can hold the clock output at a point where 500 ms worth of frequency division is completed. figs. 12-30 and 12-31 show the configuration and function of the clock timer 128 hz carry register and clock timer 8 hz carry register. fig. 12-32 shows the configuration and function of the clock timer mode register. fig. 12-30 configuration of the clock timer 128 hz carry register register flag symbol clock timer 128 hz carry register detects the state of the 128 hz carry flip-flop. reset. set. fixed to "0" upon reset power-on clock stop hold hold address read/write b 3 b 2 b 1 b 0 00 0 w t m 1 2 8 h z 1eh r & reset 0 1 ce 0000
164 m pd17068 fig. 12-31 configuration of the clock timer 8 hz carry register register flag symbol watch timer 8 hz carry register detects the state of the 8 hz carry flip-flop. reset. set. fixed to "0" upon reset power-on clock stop hold hold address read/write b 3 b 2 b 1 b 0 000 w t m 8 h z 1dh r & reset 0 1 ce 0000
165 m pd17068 fig. 12-32 configuration of the clock timer mode register register flag symbol clock timer mode register w (r/w for bit 0 only) selects the function of the p0d 0 /adc 1 /xt out and p0d 1 /adc 2 /xt in pins. operation as a port operation as a connection pin for the clock timer oscillator no output. specifies whether to output the clock timer adjustment oscillator. output from the p1b 1 /ckout. fixed to "0" specifies whether to hold the clock timer. do not hold. hold. upon reset power-on clock stop hold hold hold hold address read/write w t m h l d 0 c k o s e l x t s e l 06h 0 1 0 1 0 1 ce 000 0 0 0 b 3 b 2 b 1 b 0 12.7.3 count block the count block counts clock pulses, which are generated by the clock frequency division block, using four 8-bit counters. the clock timer consists of a seconds counter (sexagesimal), minutes counter (sexagesimal), hours counter (24-ary), days counter (septinary). these counters are reset by the reset control block (see section 12.7.4 ). each counter can be write- and read-accessed through the data buffer. figs. 12-33 to 12-35 show the configuration and function of the registers to control the count block.
166 m pd17068 fig. 12-33 configuration of the seconds and minutes set registers data buffer transfer data peripheral register register symbol peripheral address seconds set register effective data effective data counts in the seconds and minutes counters incremented at every second (or every minute for the minutes counter) with a carry generated at every 60 seconds (or every 60 minutes for the minutes counter)--sexagesimal counters. ? at read access current count in each counter ? at write access each counter is initialized. the counters must be reset before a write access. values which do not exist at a read access. if any of these values is written to the counters, their contents become undefined. fixed to "0" 8 get put dbf3 dbf2 dbf1 dbf0 don't care don't care minutes set register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 x 59 (3bh) 60 (3ch) 63 (3fh) wtmsec wtmmin 1ah 1bh 00 00
167 m pd17068 fig. 12-34 configuration of the hours set register data buffer transfer data peripheral register register symbol peripheral address hours set register effective data count in the hours counter incremented at every hour with a carry generated at every 24 hours (24-ary counter). ? at read access current count in the counter ? at write access the counter is initialized. the counter must be reset before a write access. values which do not exist at a read access. if any of these values is written to the counter, its content becomes undefined. fixed to "0" 8 get put b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 wtmhr 1ch dbf3 dbf2 dbf1 dbf0 don't care don't care 0 x 23 (17h) 24 (18h) 31 (1fh) 0 0 0
168 m pd17068 fig. 12-35 configuration of the days set register data buffer transfer data peripheral register register symbol peripheral address days set register effective data count in the days counter incremented at every day with a carry generated at every 7 days (septinary counter). ? at read access current count in the counter ? at write access the counter is initialized. the counter must be reset before a write access. values which do not exist at a read access. if any of these values is written to the counter, its content becomes undefined. fixed to "0" dbf3 dbf2 dbf1 dbf0 don't care don't care b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 00000 wtmday 1dh 0 x 6 (6h) 7 (7h) 8 get put
169 m pd17068 12.7.4 reset control block the clock timer reset register specifies whether to set or reset the clock timer. fig. 12-36 shows the configuration and function of the clock timer reset register. fig. 12-36 configuration of the clock timer reset register register flag symbol clock timer reset register specifies whether to reset the clock timer basic clock, seconds, minutes, hours, and days counters. do not reset. reset. specifies whether to reset the clock timer basic clock. do not reset. reset. do not reset. reset. do not reset. reset. specifies whether to reset the seconds, minutes, and hours counters. specifies whether to reset the days counter. hold hold power-on clock stop upon reset address read/write w t m r e s 3 w t m r e s 2 w t m r e s 1 w t m r e s 0 14h r/w 0 1 0 1 0 1 0 1 ce 0000 b 3 b 2 b 1 b 0
170 m pd17068 12.7.5 32 khz oscillator and oscillation frequency adjustment the 32 khz oscillator generates a 32 khz clock pulse for the clock timer. when using the clock timer, set the xtsel flag of the clock timer mode register to specify the p0d 0 /adc 1 / xt out and p0d 1 /adc 2 /xt in pins as the clock timer oscillator connection pins. the 32 khz clock pulse is supplied at the p1b 1 /ckout pin for oscillation frequency adjustment. to use this pin for oscillation frequency adjustment output, set the ckosel flag of the clock timer mode register. see fig. 12-32 for the configuration and function of the clock timer mode register. 12.7.6 cautions for using the clock timer (1) rewriting the counts in the counters when you want to rewrite the contents of the seconds, minutes, hours, and days counters, previously reset them. if the contents of these counters have not been reset, a normal value cannot be written to the counters when the count, such as seconds, minutes, hours, or days, is a non-zero or a nonexisting value (for example, 61 in the seconds counter). (2) reset control while the wtmresn (n = 0 to 3) is 1, the counter corresponding to the flag will not work. if you want to reset any of these counters, first set the corresponding wtmres flag to 1 and reset the counter, then reset the flag to 0 again.
171 m pd17068 13. a/d converter 13.1 outline of a/d converter fig. 13-1 outlines the a/d converter. the a/d converter compares an analog voltage applied to the adc 0 -adc 7 pins with an internal reference voltage, then converts the analog voltage to a 6-bit digital signal by evaluating the result of comparison with software. the result of comparison is detected using the adccmp flag. the successive approximation system is used for comparison. fig. 13-1 schematic diagram of a/d converter adcch2 flag adcch1 flag adcch0 flag input switching block compare block reference voltage generation block (d/a converter based on the r string method) set/reset adccmp flag adcen flag start/stop control block adc 0 p0d 0 /adc 1 /xt out p0d 1 /adc 2 /xt in p0d 2 /adc 3 p0d 3 /adc 4 p1c 0 /adc 5 p1c 1 /adc 6 p1c 2 /adc 7 6 dbf remarks 1. adcch0-2 (a/d converter channel select register bits 0 to 2): select a pin used for the a/d converter. (see fig. 13-3. ) 2. adccmp (a/d converter control register bit 0): detects the result of comparison. (see fig. 13-5. ) 3. adcen (a/d converter control register bit 3): detects comparison execution and comparison status. (see fig. 13-5. )
172 m pd17068 13.2 input switching block fig. 13-2 shows the configuration of the input switching block. the input switching block selects a pin according to the setting of the a/d converter channel select register. if the p1c 0 /adc 5 -p1c 2 /adc 7 pins are set as general-purpose output ports at this time, output signals are output on these pins and the p1c 3 pin. when any of these pins is to be used for the a/d converter, the pin must be set as an input port by using the port ic group i/o select register. in this case, the pins not used for the a/d converter and the p1c 3 pin are set as general-purpose input ports. only one pin can be used for the a/d converter at a time. port 0d contains a pull-down resistor. however, the pull-down resistor is turned off when the port is selected for the a/d converter. at this time, the pull-down resistors of the pins not selected remain on. fig. 13-3 shows the format and function of the a/d converter channel select register. fig. 13-2 configuration of input switching block adcch2 flag adcch1 flag adcch0 flag compare block adc 0 p0d 0 /adc 1 /xt out p0d 1 /adc 2 /xt in p0d 2 /adc 3 p0d 3 /adc 4 p1c 0 /adc 5 p1c 1 /adc 6 p1c 2 /adc 7 selector v adcin i/o port
173 m pd17068 fig. 13-3 format of a/d converter channel select register adc 0 pin p0d 0 /adc 1 /xt out pin p0d 1 /adc 2 /xt in pin p0d 2 /adc 3 pin p0d 3 /adc 4 pin p1c 0 /adc 5 pin p1c 1 /adc 6 pin p1c 2 /adc 7 pin selects a pin used for the a/d converter. register flag symbol b 3 b 2 b 1 b 0 address read/write 0 a d c c h 2 a d c c h 1 a d c c h 0 a/d converter channel select register 000 001 010 011 100 101 110 111 upon reset power-on clock stop ce 000 0 000 * * = hold fixed to 0 21h r/w **
174 m pd17068 13.3 compare voltage generation block and compare block fig. 13-4 shows the configuration of the reference voltage generation block and compare block. according to the 6-bit data set in the a/d converter data register, the reference voltage generation block switches between tap decoders to generate 64 types of reference voltage v ref . this means that the reference voltage generation block is a d/a converter based on the r string method. the power supply for the r string method has the same potential as v dd of the device. the compare block compares the voltage v adcin applied to a pin with the reference voltage v ref to determine which is larger. fig. 13-5 and fig. 13-6 show the formats and functions of the a/d converter control register flags and a/d converter data register. table 13-1 provides a list of reference voltages. fig. 13-4 configuration of reference voltage generation block and compare block dbf 0126263 1 2 rr r 3 2 r v adcin v ref 2 pf 1/2 v dd adccmp flag v dd adcen flag comparator a/d converter data register (adcr) tap decoder start/stop control block
175 m pd17068 fig. 13-5 format of a/d converter control register v adcin < v ref v adcin > v ref detects the result of comparison by the a/d converter. register flag symbol b 3 b 2 b 1 b 0 address read/write 0 a d c c m p a/d converter control register 0 1 upon reset power-on clock stop ce 00 0 * fixed to 0 24h r/w r for bit 0 only detects the comparison execution and comparison status of the a/d converter. 0 1 0 0 0 a d c e n in write operation no change comparison executed in read operation comparison completed comparison in progress * = undefined ** = hold ** **
176 m pd17068 fig. 13-6 format of a/d converter data register v ref = b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf1 dbf0 don't care don't care fixed to 0 data buffer transfer data peripheral register 8 register sets an a/d converter reference voltage. v ref = 0 v 0 1 x ffh valid data a/d converter data register 0 0 adcr 02h x ?0.5 64 v dd (v) get put
177 m pd17068 table 13-1 values in a/d converter data register and reference voltages data set in adcr reference voltage data set in adcr reference voltage decimal hexadecimal logical voltage when v dd = 5 v decimal hexadecimal logical voltage when v dd =5v (dec) (hex) unit: v dd v unit: v (dec) (hex) unit: v dd v unit: v 0 00h 0 0 32 20h 31.5/64 2.461 1 01h 0.5/64 0.039 33 21h 32.5/64 2.539 2 02h 1.5/64 0.117 34 22h 33.5/64 2.617 3 03h 2.5/64 0.195 35 23h 34.5/64 2.695 4 04h 3.5/64 0.273 36 24h 35.5/64 2.773 5 05h 4.5/64 0.352 37 25h 36.5/64 2.852 6 06h 5.5/64 0.430 38 26h 37.5/64 2.930 7 07h 6.5/64 0.508 39 27h 38.5/64 3.008 8 08h 7.5/64 0.586 40 28h 39.5/64 3.086 9 09h 8.5/64 0.664 41 29h 40.5/64 3.164 10 0ah 9.5/64 0.742 42 2ah 41.5/64 3.242 11 0bh 10.5/64 0.820 43 2bh 42.5/64 3.320 12 0ch 11.5/64 0.898 44 2ch 43.5/64 3.398 13 0dh 12.5/64 0.977 45 2dh 44.5/64 3.477 14 0eh 13.5/64 1.055 46 2eh 45.5/64 3.555 15 0fh 14.5/65 1.133 47 2fh 46.5/64 3.633 16 10h 15.5/64 1.211 48 30h 47.5/64 3.711 17 11h 16.5/64 1.289 49 31h 48.5/64 3.789 18 12h 17.5/64 1.367 50 32h 49.5/64 3.867 19 13h 18.5/64 1.445 51 33h 50.5/64 3.945 20 14h 19.5/64 1.523 52 34h 51.5/64 4.023 21 15h 20.5/64 1.602 53 35h 52.5/64 4.102 22 16h 21.5/64 1.680 54 36h 53.5/64 4.180 23 17h 22.5/64 1.758 55 37h 54.5/64 4.258 24 18h 23.5/64 1.836 56 38h 55.5/64 4.336 25 19h 24.5/64 1.914 57 39h 56.5/64 4.414 26 1ah 25.5/64 1.992 58 3ah 57.5/64 4.492 27 1bh 26.5/64 2.070 59 3bh 58.5/64 4.570 28 1ch 27.5/64 2.148 60 3ch 59.5/64 4.648 29 1dh 28.5/64 2.227 61 3dh 60.5/64 4.727 30 1eh 29.5/64 2.305 62 3eh 61.5/64 4.805 31 1fh 30.5/64 2.383 63 3fh 62.5/64 4.883
178 m pd17068 13.4 compare timing chart when a compare operation is completed, the adcen flag is automatically reset to 0. this means that the adcen flag is detected after the adcen flag is set, and the result of comparison (adccmp flag) is read when the adcen flag is reset. accordingly, the time required for one compare operation is three-instruction execution time (6 m s). fig. 13-7 indicates the timing chart. fig. 13-7 timing of a/d converter compare operation instruction cycle sample and hold adcen flag adccmp flag result of comparison 13.5 a/d converter performance table 13-2 indicates the performance of the a/d converter. table 13-2 performance of a/d converter 1 2 lsb 62.5 64 v dd lsb note 3 2 item performance resolution 6 bits input voltage range 0-v dd quantization error over-range errors associated with offset, gain, nonlinearity, etc. note a quantization error is included.
179 m pd17068 13.6 using a/d converter 13.6.1 comparison with one reference voltage an example of program is described below. example a comparison is made between the input voltage v adcin applied to the adc 0 pin and the reference voltage v ref ((31.5/64) v dd ). when v adcin > v ref , a branch to aaa occurs. when v adcin < v ref , a branch to bbb occurs. init: adcr7 flg 0.0eh.3 ; dummy adcr6 flg 0.0eh.2 ; dummy adcr5 flg 0.0eh.1 ; defines each bit of the data buffer as an adcr data setting flag. adcr4 flg 0.0eh.0 adcr3 flg 0.0fh.3 adcr2 flg 0.0fh.2 adcr1 flg 0.0fh.1 adcr0 flg 0.0fh.0 initflg not adcch3, not adcch2, not adcch1, not adcch0 ; sets the adc 0 pin for the a/d converter. start: initflg not adcr3, not adcr2, not adcr1, not adcr0 initflg not adcr7, not adcr6, not adcr5, not adcr4 put adcr, dbf ; sets (31.5/64) v dd as the reference voltage v ref . set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then br aaa ; branches to aaa when the result of comparison is false. br bbb ; branches to bbb when the result of comparison is true.
180 m pd17068 13.6.2 successive approximation based on the binary search method in one compare operation, the a/d converter can make a comparison with only one reference voltage. this means that successive approximation needs to be programmed for conversion of an analog voltage to a digital signal. if the processing time of a successive approximation program varies from one input voltage to another, processing of other programs may be adversely affected. in such a case, the binary search method described in (1) to (3) below is useful. (1) concept of binary search the concept of binary search is described below. first, v dd /2 is set as a reference voltage. then, a comparison is made by adding a voltage of v dd /4 when the result of comparison is true (when a higher level is applied), or subtracting a voltage of v dd /4 when the result of comparison is false (when a lower level is applied). similarly, comparisons are made sequentially adding or subtracting v dd /8, v dd /16, v dd /32, and v dd /64 in this order. if the result of comparison is false at the sixth stage, v dd /64 is subtracted finally. h l h h h h h l h l l l l l 1/2 3/4 1/4 7/8 5/8 3/8 1/8 15/16 13/16 11/16 9/16 7/16 5/16 3/16 1/16 15/16 13/16 31/32 h h h h l l l l h l h l l l l l l l l l 29/32 27/32 25/32 63/64 61/64 59/64 57/64 55/64 53/64 51/64 49/64 63/64 62/64 61/64 60/64 59/64 58/64 57/64 56/64 55/64 54/64 53/64 52/64 51/64 50/64 49/64 48/64 stage stage stage a stage ? stage ? stage ? 1/64 is subtracted when the result of comparison is false. reference voltage ( v dd ) 1 0 1
181 m pd17068 (2) flowchart of the binary search method initialization start : sets a pin to be used. adcr ? 100000b : sets the reference voltage to v dd /2. adccmp=1? : detects the result of comparison, then reset b 5 of adcr : subtracts v dd /2 from the reference voltage when the flag is set to 0. set b 4 of adcr : adds v dd /4 to the reference voltage when the flag is set to either 0 or 1. adccmp=1? : detects the result of comparison, then reset b 4 of adcr : subtracts v dd /4 from the reference voltage when the flag is set to 0. set b 3 of adcr : adds v dd /8 to the reference voltage when the flag is set to either 0 or 1. adccmp=1? : detects the result of comparison, then reset b 3 of adcr : subtracts v dd /8 from the reference voltage when the flag is set to 0. set b 2 of adcr : adds v dd /16 to the reference voltage when the flag is set to either 0 or 1. adccmp=1? : detects the result of comparison, then reset b 2 of adcr : subtracts v dd /16 from the reference voltage when the flag is set to 0. set b 1 of adcr : adds v dd /32 to the reference voltage when the flag is set to either 0 or 1. adccmp=1? : detects the result of comparison, then reset b 1 of adcr : subtracts v dd /32 from the reference voltage when the flag is set to 0. set b 0 of adcr : adds v dd /64 to the reference voltage when the flag is set to either 0 or 1. adccmp=1? : detects the result of comparison, then reset b 0 of adcr : subtracts v dd /64 from the reference voltage when the flag is set to 0. detect contents of adcr : ends conversion when the flag is set to 1. end y n y n y n y n y n y n
182 m pd17068 (3) example of program based on the binary search method (a) method with a short conversion time init: adcr7 flg 0.0eh.3 ; dummy adcr6 flg 0.0eh.2 ; dummy adcr5 flg 0.0eh.1 ; defines each bit of the data buffer as an adcr data setting adcr4 flg 0.0eh.0 ; flag. adcr3 flg 0.0fh.3 ; adcr2 flg 0.0fh.2 ; adcr1 flg 0.0fh.1 ; adcr0 flg 0.0fh.0 ; initflg not adcch3, not adcch2, not adcch1, not adcch0 ; sets the adc 0 pin for the a/d converter. start: initflg not adcr3, not adcr2, not adcr1, not adcr0 initflg not adcr7, not adcr6, not adcr5, not adcr4 put adcr, dbf ; sets (31.5/64) v dd as the reference voltage v ref . set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then clr1 adcr5 ; subtracts (32/64) v dd when the flag is set to 0. set1 adcr4 ; adds (16/64) v dd . put adcr, dbf set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then clr1 adcr4 ; subtracts (16/64) v dd when the flag is set to 0. set1 adcr3 ; adds (8/64) v dd . put adcr, dbf set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then clr1 adcr3 ; subtracts (8/64) v dd when the flag is set to 0. set1 adcr2 ; adds (4/64) v dd . put adcr, dbf set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1
183 m pd17068 skt1 adccmp ; detects the adccmp flag, then clr1 adcr2 ; subtracts (4/64) v dd when the flag is set to 0. set1 adcr1 ; adds (2/64) v dd . put adcr, dbf set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then clr1 adcr1 ; subtracts (2/64) v dd when the flag is set to 0. set1 adcr0 ; adds (1/64) v dd . put adcr, dbf set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp ; detects the adccmp flag, then clr1 adcr1 ; subtracts (1/64) v dd when the flag is set to 0. end: (b) method with a smaller number of program steps init: workr1 mem 0.01h ; workr0 mem 0.00h ; initflg not adcch3, not adcch2, not adcch1, not adcch0 ; sets the adc 0 pin for the a/d converter. start: mov dbf1, #0010b mov dbf0, #0000b mov workr1, #0110b mov workr0, #0000b clr1 cy loop: rorc work1 rorc work0 skf1 cy br end put adcr, dbf ; sets (31.5/64) v dd as the reference voltage v ref . set1 adcen ; starts comparison. skf1 adcen ; detects compare operation in progress. br $ C 1 skt1 adccmp br bbb aaa: or dbf1, work1
184 m pd17068 or dbf0, work0 br loop bbb: eor dbf1, workr1 eor dbf0, workr0 br loop end: 13.7 notes on using a/d converter when the p1c 0 /adc 5 to p1c 2 /adc 7 pins are used for the a/d converter, the pins need to be set as general- purpose input ports with the p1cgio flag. port 1c is a group i/o, so that the p1c 3 pin can be used only as a general-purpose input port when the a/d converter is used. 13.8 states upon reset 13.8.1 power-on reset the p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in , p0d 0 /adc 1 /xt out pins, and p1c 2 /adc 7 to p1c 0 /adc 5 pins are set as general-purpose input ports. 13.8.2 clock stop the p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in , p0d 0 /adc 1 /xt out pins, and p1c 2 /adc 7 to p1c 0 /adc 5 pins are set as general-purpose input ports. 13.8.3 ce reset the p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in , p0d 0 /adc 1 /xt out pins, and p1c 2 /adc 7 to p1c 0 /adc 5 pins are set as general-purpose input ports.
185 m pd17068 14. d/a converter (pwm method) 14.1 outline of d/a converter fig. 14-1 outlines the d/a converter. the d/a converter outputs a signal according to the pulse width modulation (pwm) method, which allows a variable duty cycle. by attaching an external low-pass filter, a digital signal can be converted to an analog signal. a signal with a variable duty cycle is output on each pin independently. the output frequency is 1953 hz, and the duty cycle can be changed in 256 steps. fig. 14-1 schematic diagram of d/a converter p2c 0 /pwm 0 p2c 3 /pwm 3 p2b 2 /pwm 6 p2c 1 /pwm 1 p2b 0 /pwm 4 p2b 3 /pwm 7 p2c 2 /pwm 2 p2b 1 /pwm 5 p2a 0 /pwm 8 duty cycle setting block clock generation block f pwm0 f pwm1 f pwm2 output switching block output switching block output switching block dbf 8 pwm data register (pwmr0, 3, 6) match 0 detected comparator 8-bit counter dbf 8 pwm data register (pwmr1, 4, 7) match 0 detected comparator 8-bit counter match 0 detected comparator 8-bit counter pwm data register (pwmr2, 5, 8) dbf 8
186 m pd17068 14.2 output switching block according to the pwm0sel-pwm8sel flags of pwm mode select registers 1 to 3, the output switching block determines whether each output pin of the d/a converter is to be used for the d/a converter or as a general- purpose output port. fig. 14-2 shows the configuration of the output switching block. fig. 14-3 through fig. 14-5 show the formats and functions of pwm mode select registers 1 to 3. whether to use a pin for the d/a converter or as a general-purpose output port can be set independently of other pins. each output pin is an n-ch open drain output, so that a pull-up resistor is externally required. fig. 14-2 configuration of output switching block output latch pwm0sel-pwm8sel flags each output pin 1 0 comparator output fig. 14-3 format of pwm mode select register 3 general-purpose output port d/a converter sets the function of p2a 0 /pwm 8 pin. register flag symbol b 3 b 2 b 1 b 0 address read/write 0 p w m 8 s e l pwm mode select register 3 0 1 upon reset power-on clock stop ce 000 0 0 hold fixed to 0 03h r/w 00
187 m pd17068 fig. 14-4 format of pwm mode select register 2 general-purpose output port d/a converter sets the function of p2b 0 /pwm 4 pin. register flag symbol b 3 b 2 b 1 b 0 address read/write p w m 4 s e l pwm mode select register 2 0 1 upon reset power-on clock stop ce 000 0 04h r/w p w m 5 s e l p w m 6 s e l p w m 7 s e l general-purpose output port d/a converter sets the function of p2b 1 /pwm 5 pin. 0 1 general-purpose output port d/a converter sets the function of p2b 2 /pwm 6 pin. 0 1 general-purpose output port d/a converter sets the function of p2b 3 /pwm 7 pin. 0 1 000 0 hold
188 m pd17068 fig. 14-5 format of pwm mode select register 1 general-purpose output port d/a converter sets the function of p2c 0 /pwm 0 pin. register flag symbol b 3 b 2 b 1 b 0 address read/write p w m 0 s e l pwm mode select register 1 0 1 upon reset power-on clock stop ce 000 0 05h r/w p w m 1 s e l p w m 2 s e l p w m 3 s e l general-purpose output port d/a converter sets the function of p2c 1 /pwm 1 pin. 0 1 general-purpose output port d/a converter sets the function of p2c 2 /pwm 2 pin. 0 1 general-purpose output port d/a converter sets the function of p2c 3 /pwm 3 pin. 0 1 000 0 hold 14.3 duty cycle setting block the duty cycle setting block compares the value set in each pwm data register (pwmr0-pwmr8) with the count value of each 8-bit counter with the timing of each basic clock (f pwm0 , f pwm1 , f pwm2 ). the block outputs the low level when a match with the value of a pwm data register is found. when the counter value reaches 0, the block outputs the high level with the timing of a basic clock. let x be the value set in a pwm data register. then, the duty cycle is as follows: duty cycle: d = 100% a basic clock of 500 khz is used, so that the frequency and period of an output signal are as follows: frequency: f = = . . 1.953 khz x 256 500 khz 256
189 m pd17068 period: t = = 512 m s for each pin, a different value can be set in each pwm data register through the data buffer (dbf). this means that a signal with an independent duty cycle can be output on each pin. fig. 14-6 shows the format of the pwm data registers. fig. 14-6 format of pwm data registers 256 500 khz frequency : f = b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf1 dbf0 don't care don't care data buffer transfer data peripheral register 8 register sets the pwm output duty cycle for each pin. duty ratio : d = valid data pwmr0 0ch get put pwmr1 0dh pwmr2 0eh pwmr3 0fh pwmr4 10h pwmr5 11h pwmr6 12h pwmr7 13h pwmr8 14h 0 x 255 pwm0 data register pwm1 data register pwm2 data register pwm3 data register pwm4 data register pwm5 data register pwm6 data register pwm7 data register pwm8 data register 100% x 256 khz 500 256 = 1953 hz
190 m pd17068 14.4 clock generation block the clock generation block outputs the basic clocks (f pwm0 , f pwm1 , f pwm2 ) used to set the duty cycle of each output signal. the output frequency is 500 khz for all of f pwm0 , f pwm1 , f pwm2 . fig. 14-7 shows the phase differences among the clocks. fig. 14-7 phase differences among basic clocks f pwm0 f pwm1 f pwm2 500 ns 500 ns 500 ns 500 ns 2 s 14.5 output waveforms of d/a converter the relationships between duty cycles and output waveforms are shown in (1). the output waveform on each pin is shown in (2) below. a phase difference results because of a different basic clock supplied. (1) duty cycles and output waveforms 2 s2 s 512 s 2 s x = 0 x = 1 x = 2 x = 255
191 m pd17068 (2) output waveform on each pin 1 s 500 ns 512 s pwm 0 , pwm 1 , pwm 6 (x = 1) pwm 1 , pwm 4 , pwm 7 (x = 1) pwm 2 , pwm 5 , pwm 8 (x = 1) 14.6 notes on using d/a converter (1) after turning on the power, perform initial pwm output setting according to the procedure below. the pwm data registers are undefined when the power is turned on, so that this procedure is required to set desired data beforehand. # set desired values in the pwm data registers. $ set the pwmnsel flags. (2) never rewrite the data set in a pwm data register during pwm operation. this is because an output signal with a correct duty cycle cannot be obtained during one period (512 m s). 14.7 states upon reset 14.7.1 power-on reset the p2c 0 /pwm 0 to p2a 0 /pwm 8 pins are set as general-purpose output ports. all values output at this time are undefined. the value of each pwm data register is undefined. 14.7.2 clock stop the p2c 0 /pwm 0 to p2a 0 /pwm 8 pins are set as general-purpose output ports. all values output at this time are the previous latch values. the previous value of each pwm data register is preserved. 14.7.3 ce reset the p2c 0 /pwm 0 to p2a 0 /pwm 8 pins preserve the previous output states. this means that those pins that are used for the d/a converter preserve the pwm output states. 14.7.4 halt state the p2c 0 /pwm 0 to p2a 0 /pwm 8 pins preserve the previous output states. this means that those pins that are used for the d/a converter preserve the pwm output states.
192 m pd17068 15. serial interface 15.1 general fig. 15-1 outlines the serial interface. table 15-1 shows the serial interface classes and communication modes. as shown in fig. 15-1, the serial interface consists of two systems: serial interface 0 (sio0) and serial interface 1 (sio1). serial interface 0 and serial interface 1 can be used simultaneously. serial interface 0 can use a 2-wire system or a 3-wire system. the 2-wire system uses the sda and scl pins and the 3-wire system uses the sck 0 , so 0 , and si 0 pins. with the 2-wire system, i 2 c bus or serial i/o can be selected as the communication mode. serial interface 1 can only use a 3-wire system. the pins used are sck 1 , so 1 , and si 1 . the communication mode is serial i/o. fig. 15-1 serial interface sda/p0a 0 scl/p0a 1 sck 0 /p0a 2 so 0 /p0a 3 si 0 /p0b 0 8 mhz 8 mhz irqsio0 flag irqsio1 flag serial interface 1 serial interface 0 sck 1 /p2d 0 so 1 /p2d 1 si 1 /p2d 2 presettable shift register 1 presettable shift register 0 i/o control clock control block interrupt control block i/o control clock control block
193 m pd17068 table 15-1 serial interface classes and communication modes 15.2 serial interface 0 15.2.1 general fig. 15-2 outlines serial interface 0. serial interface 0 can use a 2-wire i 2 c bus or 2-wire/3-wire serial i/o mode. fig. 15-2 serial interface 0 channel number of wires communication mode pins used serial interface 0 2-wire system i 2 c bus p0a 0 /sda serial i/o p0a 1 /scl 3-wire system serial i/o p0a 2 /sck 0 p0a 3 /so 0 p0b 0 /si 0 serial interface 1 3-wire system serial i/o p2d 0 /sck 1 p2d 1 /so 1 p2d 2 /si 1 scl/p0a 1 sck 0 /p0a 2 sio0ch flag sb flag sio0ms flag sio0ck0 and sio0ck1 flags wait signal clock counter sio0sf8 and sio0sf9 flags sio0ch flag sb flag sio0tx flag sda/p0a 0 so 0 /p0a 3 si 0 /p0b 0 ack sback flag serial data presettable shift register 0 out (sio0sfr) in sbstt and sbbsy flags sio0wrq0 and sio0wrq1 flags sio0nwt flag 8 mhz sio0imd0 and sio0imd1 flags clock i/o control block clock control block wait control block counts 8 and 9 interrupt control block start/stop detection block data i/o control block acknowledge control block
194 m pd17068 remarks 1. sio0ch (bit 3 of serial i/o-0 mode selection register: see fig. 15-3 ): 2-wire/3-wire system selection 2. sb (bit 2 of serial i/o-0 mode selection register: see fig. 15-3 ): i 2 c bus/serial i/o selection 3. sio0ms (bit 1 of serial i/o-0 mode selection register: see fig. 15-3 ): master/slave selection 4. sio0tx (bit 0 of serial i/o-0 mode selection register: see fig. 15-3 ): receive/transmit selection 5. sio0ck0 and sio0ck1 (bits 0 and 1 of serial i/o-0 clock selection register: see fig. 15-4 ): set the internal shift clock frequency. 6. sio0wrq0 and sio0wrq1 (bits 0 and 1 of serial i/o-0 wait control register: see fig. 15-7 ): set the communication wait condition. 7. sio0nwt (bit 2 of serial i/o-0 wait control register: see fig. 15-7 ): sets the start of communication. 8. sio0sf8 and sio0sf9 (bits 3 and 2 of serial i/o-0 status judge register: see fig. 15-5 ): clock counter detection 9. sbstt and sbbsy (bits 1 and 0 of serial i/o-0 status judge register: see fig. 15-5 ): i 2 c bus start condition, stop condition, and clock counter detection 10. sio0imd0 and sio0imd1 (bits 0 and 1 of serial i/o-0 interrupt mode register: see fig. 15-8 ): set the interrupt timing. 11. sback (bit 3 of serial i/o-0 wait control register: see fig. 15-7 ): acknowledge data read/write 15.2.2 clock i/o control block and data i/o control block the clock i/o control block and data i/o control block control the serial interface 0 communication mode (i 2 c bus or serial i/o), the pins used (2-wire system or 3-wire system), and the transmit and receive operations. the sio0ch and sb flags select the 2-wire/3-wire system and i 2 c bus/serial i/o, respectively. the sio0ms flag selects internal clock (master)/external clock (slave) and the sio0tx flag selects the receive (rx)/transmit (tx) operation. these flags are located in the serial i/o-0 mode selection register. fig. 15-3 shows the organization and functions of the serial i/o-0 mode selection register. table 15-2 shows the pin settings. as shown in table 15-2, to set the pins, the serial interface control flag and the i/o setting flag of each pin, must be manipulated.
195 m pd17068 fig. 15-3 organization of serial i/o-0 mode selection register register flag symbol b 3 b 2 b 1 b 0 s i o 0 c h s b s i o 0 m s s i o 0 t x 08h r/w address read/write 0 1 0 1 0 1 0 1 upon reset power-on clock stop ce 00 0 0 00 0 0 00 0 0 serial i/o0 mode selection register sets the sda/p0a 0 pin (2-wire system) and so 0 /p0a 3 pin (3-wire system) serial i/o mode. (receive "rx" and transmit "tx" operation selection) 2-wire system (sda/p0a 0 pin) 3-wire system (so 0 /p0a 3 pin) serial input (hi-z) : rx operation serial output : tx operation general-purpose port serial output : tx operation sets the shift clock to be used. i 2 c bus mode slave operation (external clock input) master operation (internal clock output) external clock input internal clock output serial i/o mode i 2 c bus or serial i/o mode selection serial i/o mode i 2 c bus mode (at this time, do not set the sio0ch flag to 1.) 2-wire system or 3-wire system selection 2-wire system 3-wire system (at this time, do not set the sb flag to 1.)
196 m pd17068 table 15-2 pin settings by control flag pin setting flag pin s i o 0 c h s b communication mode s i o 0 m s clock to be used s i o 0 t x serial i/o pin name p o a b i o 3 p o a b i o 2 p o a b i o 1 p o a b i o 0 p o b b i o 0 00 01 10 2-wire serial i/o 2-wire i 2 c bus 3-wire serial i/o 0 1 0 1 0 1 11 input (receive) 0 1 output (transmit) p0a 0 /sda p0a 1 /scl p0a 2 /sck 0 p0a 3 /so 0 p0b 0 /si 0 p0a 0 /sda p0a 1 /scl p0a 2 /sck 0 p0a 3 /so 0 p0b 0 /si 0 p0a 0 /sda p0a 1 /scl p0a 2 /sck 0 p0a 3 /so 0 p0b 0 /si 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 serial input general-purpose output port serial output external clock general-purpose output port internal clock input (receive) 0 1 general- purpose port 0 1 output (transmit) output (transmit) external internal external (slave) internal (master) external internal general-purpose i/o port general-purpose i/o port general-purpose i/o port serial input general-purpose output port serial output external clock (slave) general-purpose output port internal clock (master) general-purpose i/o port general-purpose i/o port general-purpose i/o port general-purpose i/o port general-purpose i/o port external clock general-purpose output port general-purpose input port general-purpose output port serial output serial input general-purpose output port internal clock not to be set.
197 m pd17068 15.2.3 clock control block the clock control block controls the clock generation and clock output timings when the internal clock is used (master operation). the sio0ck0 and sio0ck1 flags of the serial i/o-0 clock selection register set the internal clock frequency f sc . fig. 15-4 shows the organization and functions of the serial i/o-0 clock selection register. the shift clock output from the clock control block is valid only during master operation (sio0ms flag = 1). for the clock generation timing, see the item for each communication mode. fig. 15-4 organization of serial i/o-0 clock selection register 15.2.4 clock counter and start/stop detection block the clock counter is a wrap around counter that counts the rising edge of the clock pulses. whether the internal clock or the external clock is used cannot be judged because the clock counter reads the state of the clock pin directly. the contents of the clock counter can be detected through the sio0sf8 and sio0sf9 flags of the serial i/o-0 status judge register, but cannot be read directly by program. the start/stop detection block detects the start and stop conditions when the i 2 c bus mode is used. the start and stop conditions are detected with the sbstt and sbbsy flags of the i/o-0 status judge register. fig. 15-5 shows the organization and functions of the serial i/o-0 status judge register. for clock counter operation and timing chart, see the item for each communication mode. register flag symbol b 3 b 2 b 1 b 0 00 s i o 0 c k 1 s i o 0 c k 0 39h r/w address read/write 0 upon reset power-on clock stop ce 00 undefined hold hold 0 01 10 11 100 khz 50 khz 500 khz 1 mhz fixed to 0. serial i/o-0 clock selection register sets the serial interface 0 internal shift clock frequency f sc .
198 m pd17068 fig. 15-5 organization of serial i/o-0 status change register register flag symbol b 3 b 2 b 1 b 0 s b s t t s b b s y 28h r address read/write serial i/o0 status judge register s i o 0 s f 8 s i o 0 s f 9 i 2 c bus mode start/stop condition detection i 2 c bus mode serial i/o mode detect stop condition detect start condition 0 1 hold at "0". i 2 c bus mode start condition and clock counter detection i 2 c bus mode serial i/o mode 0 1 detect falling edge of clock when clock counter reaches "9". 0 1 0 1 detect start condition hold previous value. clock counter detection i 2 c bus mode serial i/o mode clock counter "0" or "1" detect rising edge of clock when clock counter reaches "9". clock counter "9". clock counter detection i 2 c bus mode serial i/o mode clock counter "0" or "1" detect rising edge of clock when clock counter reaches "8". clock counter "8" upon reset power-on clock stop ce 00 00 00 00 00 00
199 m pd17068 15.2.5 presettable shift register 0 presettable shift register 0 is an 8-bit shift register for writing serial out data and reading serial in data. it is written and read through a data buffer. presettable shift register 0 outputs the contents of the most significant bit (msb) to the serial data i/o pin in synchronization with the falling edge of the shift clock and reads data at the least significant bit (lsb) in synchronization with the rising edge of the shift clock. fig. 15-6 shows the organization and functions of presettable shift register 0. fig. 15-6 organization of presettable shift register 0 note if a put or get instruction is executed during serial communication, the data may be destroyed. for details, see section 15.2.10 . d7 d6 d5 d4 d3 d2 d1 d0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral register dbf3 dbf2 dbf0 don't care don't care data buffer transfer data peripheral register 8 register valid data sio0sfr 03h get note put note l s b m s b presettable shift register 0 d7 d6 d5 d4 d3 d2 d1 d0 serial out serial in dbf1 serial out data write and serial in data read
200 m pd17068 15.2.6 wait control block and acknowledge control block the wait control block controls communication wait and release. the sio0wrq0 and sio0wrq1 flags (bits 0 and 1 of the serial i/o-0 wait control register) set the wait condition. serial communication is started by setting (wait release) the sio0nwt flag (bit 2 of the serial i/o-0 wait control register). the communication state can be detected with the sio0nwt flag. when 0 is written in the sio0nwt flag in the wait released state, the wait state is set. this is called forced wait. the acknowledge control block outputs and detects the acknowledge signal when the i 2 c bus mode is used. acknowledge is written and read by the sback flag (bit 3 of the serial i/o-0 wait control register). fig. 15-7 shows the organization and functions of the serial i/o-0 wait control register.
201 m pd17068 fig. 15-7 organizations of serial i/o-0 wait control register register flag symbol b 3 b 2 b 1 b 0 s b a c k s i o 0 n w t s i o 0 w r q 1 s i o 0 w r q 0 18h r/w address read/write 0 1 upon reset power-on clock stop ce 00 0 0 00 0 0 00 0 0 0 1 0 0 1 1 0 1 0 1 serial i/o-0 wait control register wait condition setting name i 2 c bus mode serial i/o mode does not wait. no wait data wait acknowledge wait not to be set. the wait state is set by the falling edge of the shift clock when the clock counter reaches "8". the wait state is set by the rising edge of the shift clock when the clock counter reaches "8". the wait state is set by the falling edge of the shift clock when the clock counter reaches "9". the wait state is set by the rising edge of the shift clock when the clock counter reaches "9". falling edge of clock when clock counter reaches "8" after start condition detected. address wait wait setting and wait state detection when flag written when flag read forced wait release wait (serial communication start) wait according to the condition specified with the sio0wrq0 and sio0wrq1 flags in serial communication i 2 c bus mode acknowledge signal setting and detection i 2 c bus mode at reception (sio0tx = 0) at transmission (sio0tx = 1) serial i/o mode output "0" as acknowledge output "1" as acknowledge detect slave acknowledge (acknowledge = "0") detect slave acknowledge (acknowledge = "1") no operation. therefore, can be used for other purposes.
202 m pd17068 15.2.7 interrupt control block in the interrupt control block, the serial i/o-0 interrupt mode register specifies the condition at which an interrupt request is issued. when the interrupt request condition is established, the irqsio0 flag is set. change the interrupt condition in the wait state. if the interrupt condition is changed in the wait released state, an interrupt request may be issued at the time the condition is changed. fig. 15-8 shows the organization and functions of the serial i/o-0 interrupt mode register. fig. 15-8 organization of serial i/o-0 interrupt mode register notes 1. if this mode is set when the clock counter count is 7, an interrupt request is issued. 2. if this mode is set when the clock counter count is 8, an interrupt request is issued. 3. if this mode is set when the sbstt flag is 1 and the clock counter count is 7, an interrupt request is issued. 4. if this mode is set after the stop condition has been specified, an interrupt request is issued. register flag symbol b 3 b 2 b 1 b 0 00 s i o i m d 1 s i o i m d 0 38h r/w address read/write 0 upon reset power-on clock stop ce 00 undefined hold hold 0 01 10 11 fixed to 0. serial i/o-0 interrupt mode register sets the interrupt request condition. i 2 c bus mode serial i/o mode rising edge of shift clock when clock counter reaches "7". rising edge of shift clock when clock counter reaches"7". note 1 rising edge of shift clock when clock counter reaches"8". rising edge of shift clock when clock counter reaches "8". note 2 rising edge of shift clock when clock counter reaches"7" after start condition detected. note 3 when stop condition detected. note 4 interrupt request not issued.
203 m pd17068 15.2.8 i 2 c bus mode (1) general the i 2 c bus mode communicates with 2-wires: scl pin and sda pin. it has the following features: l communication can be controlled by start/stop conditions and 9th clock acknowledge. l the communication wait state can be set by externally fixing the clock at a low level by using the n-ch open drain pin. (2) timing chart fig. 15-9 is the timing chart. fig. 15-9 i 2 c bus mode timing chart remarks # start condition generation by general-purpose i/o port $ master transmit state setting % wait release & wait timing at address wait and data wait setting ( wait timing at acknowledge wait setting ) stop condition generation by general-purpose i/o port ) , * , + interrupt request timing start condition stop condition shift clock serial data clock counter sio0nwt sio0sf8 sio0sf9 sbstt sbbsy 123 789 la d7 d6 d5 d1 d0 ack 12 067891
204 m pd17068 (3) clock counter operation the clock counter initial value is 0. thereafter, the clock counter is incremented each time the rising edge of the clock pin signal is detected. when the clock counter reaches 9, it returns to 1 and continues counting. the clock counter reset conditions are: # power-on reset $ clock-stop instruction execution % start condition detection & communication mode switched from i 2 c bus mode to 2-wire or 3-wire serial i/o mode ( ce reset (4) wait operation and cautions when the wait state is released, serial data is immediately output (at transmit operation) and the serial interface remains in the wait released state until the condition set by the sio0wrq0 and sio0wrq1 flags is satisfied. when the wait condition is satisfied, the shift clock pin is made low level and operation of the clock counter and presettable shift register 0 is stopped. note that if data is written into presettable shift register 0 while the serial interface is in the released state and the shift clock pin is low level, the data may not be written correctly. if forced wait is specified in the wait released state, the forced wait state is set at the falling edge of the next clock pulse after 0 is written in the sio0nwt flag. the wait released state is not changed even if wait release is specified again in that state. note that when forced wait is specified in the wait state, one shift clock is output. when using the i 2 c bus mode, do not set the data wait condition (sio0wrq0 = 1, sio0wrq1 = 0) consecutively. this is because when the data wait condition is set twice in succession to release the wait state, the wait state will be immediately set when it is released for the second time. when the shift clock output pin is externally forced to low level while it is at high level during master operation (this is called wait request from a slave), master operation is set to the wait state. in this case, operation restarts at the time the slave wait request is cleared. (5) interrupt request timing the interrupt request timing can be selected with the sio0imd0 and sio0imd1 flags.
205 m pd17068 (6) acknowledge block and its operation the acknowledge block operates only when the i 2 c bus mode is used. it is used in receive operation acknowledge signal output and transmit operation acknowledge signal detection. during the receive operation, the contents of the sback flag are output from the serial data pin at the falling edge of the shift clock when the clock counter reaches 8. during the receive operation, once data is set in the sback flag, that value is held. during the transmit operation, the state of the serial data pin is read at the sback flag at the rising edge of the shift clock when the clock counter reaches 9. fig. 15-10 shows the acknowledge output and input operations. during the receive operation, set acknowledge (sback flag setting) simultaneously with release of the wait state (sio0nwt flag setting). this is because the sback and sio0nwt flags are included in the same register. as a result, if only the sback flag is set, the sio0nwt flag is also set. if the serial interface is in the wait state, the wait state is released in the wait state and one shift clock is output. fig. 15-10 acknowledge output and input operations l receive operation l transmit operation shift clock data 78 9 hi-z (d1) hi-z (d0) sback output hi-z data input acknowledge output wait release must be set at the same time. shift clock data 78 9 data output acknowledge input d1 output d0 output receiving side ack
206 m pd17068 (7) shift clock generation timing in i 2 c bus mode (a) when the initial state is released initial state refers to the time that i 2 c bus method master operation is selected. while the serial interface is in the wait state, low level is output from the shift clock pin. fig. 15-11 shift clock generation timing in i 2 c bus mode (1/5) (b) when wait operation is performed # # when the interface enters the wait state when the condition specified with the sio0wrq0 and sio0wrq1 flags is satisfied (normal operation) fig. 15-11 shift clock generation timing in i 2 c bus mode (2/5) $ $ when forced wait is set in the wait state nothing changes. shift clock 1 : 1 1/f sc wait state initialization wait release shift clock 1/f sc wait time wait released state wait caused by sio0wrq1 and sio0wrq0 wait release
207 m pd17068 % % when forced wait is set in the wait released state the wait state is set at the falling edge of the next clock after forced wait is set. however, operation of the clock counter and presettable shift register 0 is stopped at the time force wait is set. when forced wait is set when the clock pin is low level, the clock counter and presettable shift register 0 operate for one clock. fig. 15-11 shift clock generation timing in i 2 c bus mode (3/5) & & when wait release is specified in wait released state nothing changes. ( ( when a slave issued a wait request in wait released state the clock is output at the timing shown in fig. 15-11 (4/5) after the slave wait request is cleared. the values of t 1 and t 2 in the table are: fig. 15-11 shift clock generation timing in i 2 c bus mode (4/5) l if wait request is issued when the scl pin is at low level f sc t 1 t 2 50 khz 0 to 10 m s 1 to 10 m s 100 khz 0 to 5 m s 1 to 5 m s 500 khz 0 to 1 m s 0.5 to 1 m s 1 mhz 0 to 687.5 ns 187.5 to 500 ns shift clock shift clock 1/f sc 1/f sc wait time wait hold wait released state forced wait caused by sio0nwt wait release wait hold wait time forced wait caused by sio0nwt wait release 1/f sc slave wait request wait release state shift clock t 1 t 2 slave wait request clear
208 m pd17068 remark if the slave wait request is cleared before the next rising edge of the scl pin signal, wait is not recognized and operation continues. l if wait request is issued when the scl pin is at high level (c) slave (external clock) operation at the first slave operation setting after the power supply voltage v dd is turned on, the scl pin output is undefined. at this time, if the scl pin is externally set to low level, it outputs low level until the next time the wait state is released. fig. 15-11 shift clock generation timing in i 2 c bus mode (5/5) (8) start/stop conditions and sbstt and sbbsy flags operation fig. 15-12 shows the fetch timing of the start and stop conditions. to fetch the start and stop conditions correctly, the shift clock must satisfy the states indicated in the figure for at least 1 m s (t 3 and t 4 ) before and after the edges of the serial data. when this condition is satisfied, the sbstt and sbbsy flags change 2 m s after the edges. the sbstt and sbbsy flags operate only when the i 2 c bus mode is used. the communication state of the other station can be detected by detecting these flags. these flags operate without regard to master, slave, receiving, transmitting, waiting, or wait released. for the serial i/o mode, 0 is held. for a description of sbstt flag and sbbsy flag operation, see fig. 15-9. shift clock 1/f sc t 1 t 2 slave wait request clear slave wait request shift clock i/o port wait time (originally hi-z) wait release time slave set wait release
209 m pd17068 fig. 15-12 start/stop conditions fetch timing (a) start condition fetch timing note t 3 and t 4 must be at least 1 m s. (b) stop condition fetch timing note t 3 and t 4 must be at least 1 m s. remark fig. 15-12 (a) and (b) indicate the timings with a clock frequency of 8 mhz. shift clock pin h l h l h l t 3 t 4 2 s serial data pin sbstt, sbbsy shift clock pin h l h l h l t 3 t 4 2 s serial data pin sbbsy
210 m pd17068 15.2.9 serial i/o mode (1) general in the serial i/o mode, communication is performed with the 2-wire system, which uses the scl and sda pins, on with the 3-wire system, which uses the sck 0 , so 0 , and si 0 pins. (2) timing chart fig. 15-13 is the serial i/o mode timing chart. fig. 15-13 serial i/o mode timing chart note sio0sf8 and sio0sf9 are also reset when the i/o-0 wait control register is written. remarks # master transmit state setting $ wait release % wait timing at address wait and data wait setting & wait timing at acknowledge wait setting ( , ) interrupt timing shift clock serial data clock counter sio0nwt sio0sf8 sio0sf9 sbstt sbbsy note 123 789 1 la d7 d6 d5 d1 d0 d7 d7 01267891 "0" "0"
211 m pd17068 (3) clock counter operation the clock counter initial value is 0. thereafter, the clock counter is incremented each time the rising edge of the clock pin signal is detected. when the clock counter reaches 9, it returns to 1 and continues counting. the clock counter reset conditions are: # power-on reset $ clock-stop instruction execution % data written to serial i/o-0 wait control register & communication mode switched from 2-wire or 3-wire serial i/o mode to i 2 c bus mode ( ce reset (4) wait operation and cautions if the wait state is released, serial data is output (at transmit operation) at the falling edge of the next clock and the serial interface remains in the wait released state until the condition set with the sio0wrq0 and sio0wrq1 flag is satisfied. when the wait condition is satisfied, the shift clock pin is made high level and operation of the clock counter and presettable shift register 0 is stopped. note that if data is written and read to and from presettable shift register 0 while the serial interface is in the wait released state and the shift clock pin is high level, the data will not be written correctly. if data is written into presettable shift register 0 while the serial interface is in the wait released state and the shift clock pin is low level, the contents of msb is output from the serial data output pin when the put instruction is executed. if forced wait is set in the wait released state, the wait state is set as soon as 0 is written in the sio0nwt flag. note that if wait release is set again in the wait released state, the clock counter will be reset. (5) interrupt request timing the interrupt request timing can be selected with the sio0imd0 and sio0imd1 flags. see section 15.2.7 . (6) acknowledge block and its operation the acknowledge block operates only when the i 2 c bus mode is used. (7) serial i/o shift clock generation timing (a) when the initial state is released initial state refers to the time when serial i/o internal clock operation is selected. during the wait state, high level is output from the shift clock pin.
212 m pd17068 shift clock 1/f sc wait state initialization wait release 1 : 1 shift clock 1/f sc wait state wait released state wait caused by sio0wrq1 and sio0wrq0 wait release shift clock wait time wait time forced wait by sio0nwt fig. 15-14 shift clock generation timing in serial i/o mode (1/4) (b) when wait operation is performed # # when the interface enters the wait state when the condition specified with the sio0wrq0 and sio0wrq1 flags is satisfied (normal operation) fig. 15-14 shift clock generation timing in serial i/o mode (2/4) $ $ when forced wait is set in the wait state fig. 15-14 shift clock generation timing in serial i/o mode (3/4)
213 m pd17068 % % when forced wait is set in the wait released state after forced wait release, the clock pulses are output at the specified period after the remaining clock pulses are output. t 5 is equal to t 6 . however, when a clock faster than the shift clock is selected, t 5 does not equal t 6 and becomes 0 t 6 500 ns. fig. 15-14 shift clock generation timing in serial i/o mode (4/4) & & when wait is released in the wait released state the clock output waveform does not change. note that the clock counter is reset. (8) sbstt and sbbsy flags operation the sbstt and sbbsy flags operate only when the i 2 c bus mode is used. for the serial i/o mode, these flags are held at 0. shift clock 1/f sc wait released state forced wait by sio0nwt wait release shift clock wait time t 6 forced wait by sio0nwt wait release t 5 falling edge of clock when there was no wait request wait released state t 5 t 6 1/f sc wait time rising edge of clock when there was no wait request
214 m pd17068 state at put/ state of shift i 2 c bus mode serial i/o mode get execution clock pin wait read (get) l fixed at low level normal read normal read state in the i 2 c bus mode write (put) l fixed at high level normal write normal write in the serial i/o the contents of the msb is out- the contents of the msb is out- mode put the next time the wait state put at the falling edge of the shift is released. (at transmit clock pin signal while the wait operation) state is released next time. (at transmit operation) wait read (get) high level normal read normal read low level normal read normal read write (put) high level normal write normal write the contents of the msb is out- the contents of the msb is out- put when the clock falls. the put when the clock falls. the clock counter is not reset. clock counter is not reset. low level not written normally. not written normally. the contents of sio0sfr are the contents of sio0sfr are destroyed. destroyed. 15.2.10 data write and read cautions data is written to presettable shift register 0 with the put sio0sfr, dbf instruction. data is read with the get dbf, sio0sfr instruction. write and read data in the wait state. if data is written and read in the wait released state, the correct data may not be written and read, depending on the state of the shift clock pin. the data write and read timing and cautions are given below. table 15-3 presettable shift register 0 data read and write operations and cautions h l 1 0 msb clock data put sio0sfr, dbf wait release put sio0sfr, dbf wait release h l 1 0 clock data msb h l 1 0 msb clock data put sio0sfr, dbf h l 1 0 msb clock data put sio0sfr, dbf released state
215 m pd17068 15.2.11 serial interface 0 operation tables 15-4 through 15-6 outline operation for each communication mode. table 15-4 i 2 c bus mode operation operation mode i 2 c bus mode slave operation (sio0ms = 0) master operation (sio0ms = 1) item receive (sio0tx = 0) transit (sio0tx = 1) receive (sio0tx = 0) transit (sio0tx = 1) state of sda/p0a 0 when poabi00 = 0 , is outputs the contents when p0abio0 = 0 , is outputs the contents each pin floating and waiting of sio0sfr at the floating and waiting of sio0sfr at the for external data input falling edge of the for external data input falling edge of the when p0abio0 = 1 , external clock when p0abio0 = 1 , external clock works as a general- regardless of p0abio0. works as a general- regardless of p0abio0. purpose output port purpose output port and outputs the con- and outputs the con- tents of the output tents of the output latch. latch. scl/p0a 1 when p0abio0 = 0 , is floating and waiting outputs the internal clock regardless of for external data input p0abio1. when p0abio0 = 1 , works as a general- purpose output port and outputs the con- tents of the output latch. clock counter incremented at the rising edge of the scl pin signal. presettable output not output shifts and outputs the not output shifts and outputs the shift register data from the msb data from the msb 0 operation each time the scl pin each time the scl pin signal falls. signal falls. input shifts and inputs the data from the lsb each time the scl pin signal rises. wait waiting outputs low level outputs low level outputs low level outputs low level operation from the scl pin. from the scl pin. from the scl pin. from the scl pin. sda pin: floating sda pin: state held sda pin: floating sda pin: state held wait scl pin: floating scl pin: floating scl pin: outputs the scl pin: outputs the released and waiting for and waiting for internal clock. internal clock. external clock input external clock input sda pin: floating sda pin: outputs sda pin: floating sda pin: outputs and waiting for data each time the and waiting for data each time the external data scl pin signal falls. external data scl pin signal falls. acknowledge ack output at the ack fetched at the ack output at the ack fetched at the falling edge of the rising edge of the 9th falling edge of the rising edge of the 8th clock. clock 8th clock. 9th clock.
216 m pd17068 table 15-5 2-wire serial i/o operation operation mode 2-wire serial i/o mode slave operation (sio0ms = 0) master operation (sio0ms = 1) item receive (sio0tx = 0) transit (sio0tx = 1) receive (sio0tx = 0) transit (sio0tx = 1) state of sda/p0a 0 when p0abio0 = 0 , is outputs the contents when p0abio0 = 0 , is outputs the contents each pin floating and waiting of sio0sfr at the floating and waiting of sio0sfr at the for external data input falling edge of the for external data input falling edge of the when p0abio0 = 1 , external clock when p0abio0 = 1 , external clock works as a general- regardless of p0abio0. works as a general- regardless of p0abio0. purpose output port. purpose output port outputs the con- and outputs the con- tents of the output tents of the output latch. latch. scl/p0a 1 when p0abio0 = 0 , is floating and waiting outputs the internal clock regardless of for external data input p0abio1. when p0abio0 = 1 , works as a general- purpose output port. outputs the con- tents of the output latch. clock counter incremented at the rising edge of the scl pin signal. presettable output not output shifts and outputs the not output shifts and outputs the shift register data from the msb data from the msb 0 operation each time the scl pin each time the scl pin signal falls. signal falls. input shifts and inputs the data from the lsb each time the scl pin signal rises. wait waiting scl pin: floating scl pin: floating scl pin: floating scl pin: floating operation sda pin: floating sda pin: state held sda pin: floating sda pin: state held wait scl pin: floating scl pin: floating scl pin: outputs the scl pin: outputs the released and waiting for and waiting for internal clock. internal clock. external clock input external clock input sda pin: floating sda pin: outputs sda pin: floating sda pin: outputs and waiting for data each time the and waiting for data each time the external data scl pin signal falls. external data scl pin signal falls.
217 m pd17068 table 15-6 3-wire serial i/o operation operation mode 3-wire serial i/o mode slave operation (sio0ms = 0) master operation (sio0ms = 1) item receive (sio0tx = 0) transit (sio0tx = 1) receive (sio0tx = 0) transit (sio0tx = 1) state of sck 0 /p0a 2 when p0abio2 = 0 , is floating and waiting outputs the internal clock regardless of each pin for external data input p0abio2. when p0abio2 = 1 , works as a general- purpose output port. outputs the contents of the output latch. so 0 /p0a 3 when p0abio3 = 0 , outputs the contents when p0abio3 = 0 , outputs the contents works as a general- of sio0sfr at the works as a general- of sio0sfr at the purpose input port falling edge of the purpose input port falling edge of the and is floating external clock and is floating external clock when p0abio3 = 1 , regardless of p0abio3. when p0abio3 = 1 , regardless of p0abio3. works as a general- works as a general- purpose output port purpose output port and outputs the con- and outputs the con- tents of the output tents of the output latch. latch. si 0 /p0b 0 when p0bbio0 = 0 , is floating and waiting for external data input when p0bbio0 = 1 , works as a general- purpose output port. outputs the contents of the output latch. clock counter incremented at the rising edge of the sck 0 pin signal. presettable output not output shifts and outputs the not output shifts and outputs the shift register data from the msb data from the msb 0 operation each time the sck 0 pin each time the sck 0 pin signal falls. signal falls. input shifts and inputs the data from the lsb each time the sck 0 pin signal rises. wait waiting sck 0 pin: floating sck 0 pin: floating sck 0 pin: high level sck 0 pin: high level operation so 0 pin: general- so 0 pin: state held output output purpose port si 0 pin: floating so 0 pin: general- so 0 pin: state held si 0 pin: floating purpose port si 0 pin: floating si 0 pin: floating wait sck 0 pin: floating sck 0 pin: floating sck 0 pin: outputs sck 0 pin: outputs released and waiting for and waiting for the internal clock. the internal clock. external clock input external clock input so 0 pin: general- so 0 pin: data output so 0 pin: general- so 0 pin: data output purpose port si 0 pin: floating and purpose port si 0 pin: floating and si 0 pin: floating and waiting for external si 0 pin: floating and waiting for external waiting for external data waiting for external data data
218 m pd17068 15.2.12 state when serial interface 0 is reset (1) power-on reset all the pins are set to general-purpose input ports. the contents of presettable shift register 0 are undefined. (2) clock-stop all the pins are set to general-purpose input ports. the contents of presettable shift register 0 retain their previous value. (3) halt all the terminals remain in their set states. the internal clock stops output when a halt instruction is executed. the external clock operates.
219 m pd17068 sck 1 /p2d 0 so 1 /p2d 1 si 1 /p2d 2 sio1hiz flag sio1ts flag clock counter irqsio1 flag presettable shift register 1 out (sio1sfr) in 8 mhz wait signal sio1ck0 and sio1ck1 flags clock i/o control block clock control block data i/o control block wait control block count value 8 15.3 serial interface 1 15.3.1 general fig. 15-15 outlines serial interface 1. serial interface 1 uses the 3-wire serial i/o mode. fig. 15-15 serial interface 1 remarks 1. sio1ck0 and sio1ck1 (bits 0 and 1 of the serial i/o-1 mode selection register: see fig. 15-16 ) sets the shift clock. 2. sio1ts (bit 3 of the serial i/o-1 mode selection register: see fig. 15-16 ) selects communication operation start/stop. 3. sio1hiz (bit 2 of the serial i/o-1 mode selection register: see fig. 15-16 ) selects the function of the so 1 /p2d 1 pins. 15.3.2 clock i/o control block and data i/o control block the clock i/o control block and data i/o control block control the serial interface 1 transmit and receive operations and select the shift clock. the sio1ck0 and sio1ck1 flags select internal clock (master) or external clock (slave) operation. the sio1hiz flag selects if the so 1 pin is used as serial data output. the flags that control the clock i/o control block and data i/o control block are located in the serial i/o-1 mode selection register. fig. 15-16 shows the organization and functions of the serial i/o-1 mode selection register. table 15-7 shows the setting state of each pin. as shown in table 15-7, to set each pin, the serial interface control flag and the i/o setting flag of each pin must be manipulated.
220 m pd17068 fig. 15-16 configuration of serial i/o-1 mode selection register 15.3.3 clock counter the clock counter is a wrap-around counter that counts the rising edge of the clock pulses. the clock counter reads the state of the clock pin directly. therefore, whether the clock is internal clock or external clock cannot be judged. the contents of the clock counter cannot be directly read by program. register flag symbol b 3 b 2 b 1 b 0 s i o 1 c k 1 s i o 1 c k 0 1ch r/w address read/write 0 upon reset power-on clock stop ce 00 0 01 10 11 external clock input 100 khz 500 khz 1 mhz 00 00 00 00 00 0 1 0 1 selects the serial interface 1 shift clock. s i o 1 t s s i o 1 h i z serial i/o-1 mode selection register selects the function of the p2d 1 /so 1 pins. general-purpose i/o port serial data output pin selects serial communication operation start/stop. operation stop (wait state) operation start
221 m pd17068 table 15-7 setting of each pin by control flag flag pin communication mode s i o 1 h i z sio1 pin setting s i o 1 c k 1 s i o 1 c k 0 clock setting pin name p 2 d b i o 2 p 2 d b i o 1 p 2 d b i o 0 pin setting 3-wire serial i/o waiting : general-purpose input port wait released : external clock input wait 0 1 0 1 0 1 0 1 0 1 general- purpose port 0 serial output 1 so 1 /p2d 1 si 1 /p2d 2 sck 1 /p2d 0 waiting : general-purpose output port wait released : general-purpose output port waiting : outputs high level. wait released : serial data output external clock internal clock general-purpose input port general-purpose output port waiting : outputs high level. wait released : internal clock output serial data input general-purpose output port 0 0 1 0 0 1 1 1
222 m pd17068 15.3.4 presettable shift register 1 presettable shift register 1 is an 8-bit shift register for writing serial out data and reading serial in data. presettable shift register 1 writes and reads data through a data buffer. presettable shift register 1 outputs (at transmit operation) the contents of the most significant bit (msb) to the serial data i/o pin in synchronization with the falling edge of the shift clock and reads data at the least significant bit (lsb) in synchronization with the rising edge of the shift clock. fig. 15-17 shows the organization and functions of presettable shift register 1. fig. 15-17 configuration of presettable shift register 1 note if a put or get instruction is executed during serial communications, the data may be destroyed. for details, see section 15.3.7 . 15.3.5 wait control block the wait control block controls communication wait and its release. serial communication is started by setting wait release at the sio1ts flag of the serial i/o-1 mode selection register. then, wait is released. wait is set again 8 clocks after communication started. the communication state can be sensed with the sio1ts flag. in short, the communication state can be sensed by detecting the state of the sio1ts flag after it is set to 1. when 0 is written in the sio1ts flag in the wait released state, the wait state is set. this is called forced wait. for the organization and functions of the serial i/o-1 mode selection register, see fig. 15-16 . d7 d6 d5 d4 d3 d2 d1 d0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral register dbf3 dbf2 dbf0 don't care don't care data buffer transfer data peripheral register 8 register valid data sio1sfr 07h get note put note l s b m s b presettable shift register 1 d7 d6 d5 d4 d3 d2 d1 d0 serial out serial in dbf1 serial out data write and serial in data read
223 m pd17068 15.3.6 serial interface 1 operation (1) timing chart fig. 15-18 shows the timing chart. fig. 15-18 serial interface 1 timing chart remarks # master transmit state setting (sio1hiz=1) $ wait release % wait timing & interrupt timing caution as shown in fig. 15-18, serial data output pin so 1 outputs high level after the end of serial data transfer. the time until high level is output is (when the main clock is 8 mhz for both # and $ ): # when internal clock selected as shift clock source t = 312.5 ns $ when external clock selected as shift clock source 312.5 3 t 3 125 ns (2) clock counter operation the clock counter initial value is 0, and is incremented each time the rising edge of the clock pin signal is detected thereafter. when the clock counter reaches 8, it returns to 1 and continues counting. the clock counter reset conditions are: # power-on reset $ clock-stop instruction execution % 0 was written in the sio1ts flag & rising edge of shift clock when clock counter reaches 8 in the wait released state ( ce reset shift clock serial data clock counter 123 78 la d7 d6 d5 d1 d0 01267 t 1 d7 sio1ts
224 m pd17068 (3) wait operation and cautions when the wait state is released, serial data is output (at transmit operation) at the falling edge of the next clock and serial interface 1 remains in the wait released state for 8 clocks. after 8 clocks are output, the shift clock pin is made high level and clock counter and presettable shift register 1 operation stops. note that if presettable shift register 1 is written or read when the serial interface is in the wait released state and the shift clock pin is high level, the data may not be set correctly. if presettable shift register 1 is written or read when the serial interface is in the wait released state and the shift clock pin is low level, the contents of the msb are output from the serial data output pin when a put instruction is executed. if forced wait is set in the wait released state, serial interface 1 enters the wait state as soon as 0 is written in the sio1ts flag. note that if wait release is set again in the wait released state, the clock counter is reset. (4) interrupt request timing an interrupt request is issued when 8 clocks are transmitted (received). (5) shift clock generation timing (a) when the initial state is released initial state refers to the time when internal clock operation is selected and the p2d 0 /sck 1 pin is set to high level. during the wait state, high level is output from the shift clock pin. wait can be released and the clock can be selected simultaneously. fig. 15-19 serial interface 1 shift clock generation timing (1/4) 1 : 1 1/f sc t x wait state initialization wait release shift clock
225 m pd17068 (b) when wait operation is performed # # when wait is set at 8th clock (normal operation) fig. 15-19 serial interface 1 shift clock generation timing (2/4) $ $ when forced wait is set in wait state fig. 15-19 serial interface 1 shift clock generation timing (3/4) % % when forced wait is set in wait released state fig. 15-19 serial interface 1 shift clock generation timing (4/4) caution the value of t x in fig. 15-19 is normally 187.5 ns. however, when 1 mhz is selected as the serial clock, t x becomes 687.5 ns (187.5 + 500 ns). & & when wait release is specified in wait released state the clock output waveform does not change. the clock counter is not reset either. however, do not change the clock frequency in the wait released state. 1/f sc t x wait state wait wait release shift clock wait released state shift clock wait time wait time forced wait by sio1ts 1/f sc t x wait state forced wait by sio1ts wait release 1/f sc t x wait state forced wait by sio1ts wait state wait released state wait released state shift clock shift clock
226 m pd17068 15.3.7 data write and data read cautions data is written to presettable shift register 1 with the put sio1sfr, dbf instruction. data is read from presettable shift register 1 with the get dbf, sio1sfr instruction. write and read data in the wait state. in the wait released state, the data may not be set and read correctly, depending on the state of the shift clock pin. the data write and read timing and cautions are given below. table 15-8 presettable shift register 1 data read and data write operations and cautions state clock data put sio1sfr, dbf wait release msb state at put/get state of shift clock pin operation of presettable shift register 1 execution wait read (get) normal read write (put) l floating when an external normal write clock is used the contents of the msb is output the next time the wait state l high level output when is released. (at transmit operation) the internal clock is used (if the clock pin is low level in the wait state when an external sio1sfr are destroyed.) clock is used, data is not written normally. the contents of wait read (get) high level normal read low level normal read write (put) high level normal write outputs the contents of the msb at the falling edge of the shift clock. the clock counter is not reset. low level not written normally. the contents of sio1sfr are destroyed. released state clock data put sio1sfr, dbf msb
227 m pd17068 15.3.8 serial interface 1 operation table 15-9 summarizes serial interface 1 operation. table 15-9 serial interface 1 operation operation mode serial interface 1 slave operation master operation item (both sio1ck1 and sioick0 are 0) (both sio1ck1 and sio1ck0 are not 0) state of sck 1 /p2d 0 waiting wait released waiting wait released each pin (sio1ts = 0) (sio1ts = 1) (sio1ts = 0) (sio1ts = 1) l when p2dbio0 = 0 , l when p2dbio0 = 0 , outputs high level outputs the internal works as a general- is floating and wait- regardless of p2dio0. clock regardless of purpose input port, ing for external clock when the state of the p2dbio0. and is floating. input. pin is read at this when the state of the l when p2dbio0 = 1 , l when p2dbio0 = 1 , time, the contents of pin is read at this works as a general- works as a general- the output latch are time, the contents of purpose output port. purpose output port. read. the output latch are outputs the con- outputs the con- read. tents of the output tents of the output latch. latch. so 1 /p2d 1 sio1hiz = 0 l when p2dbio1 = 0 , works as a general-purpose input port and is floating. l when p2dbio1 = 1 , works as a general-purpose output port. outputs the contents of the output latch. sio1hiz = 1 outputs high level re- outputs serial data re- outputs high level re- outputs serial data re- gardless of p2dbio1. gardless of p2dbio1. gardless of p2dbio1. gardless of p2dbio1. when the state of the when the state of the when the state of the when the state of the pin is read at this pin is read at this pin is read at this pin is read at this time, the contents of time, the contents of time, the contents of time, the contents of the output latch are the output latch are the output latch are the output latch are read. read. read. read. si 1 , p2d 2 l when p2dbio2 = 0 , is floating and waiting for external data input. l when p2dbio2 = 1 , works as a general-purpose output port. outputs the contents of the output latch. clock counter incremented at the rising edge of the sck 1 pin signal. presettable output l when p2dbio2 = 0 , not output. shift register l when p2dbio2 = 1 , shifts and outputs the data from the so 1 pin from the msb at the 1 operation falling edge of the sck 1 pin signal. input shifts and inputs the data from the lsb at the rising edge of the sck 1 pin signal regardless of p2dbio2. however, when p2dbio2 = 1, outputs the contents of the output latch from the si 1 pin.
228 m pd17068 15.3.9 state when serial interface 1 is reset (1) at power-on reset all the pins are set to general-purpose input ports. the contents of presettable shift register 1 are undefined. (2) at clock-stop all the pins are set to general-purpose input ports. the contents of presettable shift register 1 retain their previous state. (3) at ce reset all the pins are set to general-purpose input ports. the contents of presettable shift register 1 retain their previous state. (4) at halt all the pins retain their set states. the internal clock stops output when a halt instruction is executed. if an external clock is used, operation continues even if a halt instruction is executed.
229 m pd17068 16. image display controller (idc) the idc is used to display the channel no., volume, timer clock, etc. on a tv screen. 16.1 general 16.1.1 configuration fig. 16-1 outlines the idc. the display pattern is set in the crom (character rom) area by program. the vram (video ram) stores the data for selecting the actual display pattern from the crom. vram is allocated to bank2 of the data memory. (see fig. 4-2 .) fig. 16-1 idc remarks 1. idcen (bit 0 of idc enable register: see fig. 16-2 ) sets idc display on/off. 2. idcisel (bit 2 of idc mode selection register: see fig. 16-3 ) selects the pob 2 /i pin function. 3. idcd14sl (bit 1 of idc mode selection register: see fig. 16-3 ) sets the number of vertical dots of the display character. 4. idccpch (bit 0 of idc mode selection register: see fig. 16-3 ) sets whether or not there is a space between display characters. 5. idcbken (bit 3 of idc background selection register: see fig. 16-4 ) sets whether or not a screen background is displayed. 6. idcbkr, idcbkg, and idcbkb (bits 2, 1 and 0 of idc background selection register: see fig. 16-4 ) set the screen background color. 7. vramsel (bit 3 of idc mode selection register: see fig. 16-3 ) sets whether or not there is a vram area. idcen flag idcisel flag idcd14sl flag idccpch flag idcbken flag idcbkr flag idcbkg flag idcbkb flag h sync v sync red green blue blank p0b 2 /i dbf 10 vram pointer irqidcvp flag control data vram character pattern data vramsel flag crom dbf 8 address read addressing idc display control block idc start position control block
230 m pd17068 16.1.2 idc functions table 16-1 summarizes the idc functions. table 16-1 idc functions item function operation data number of display maximum 192 characters/screen (full screen possible characters by program) display position adjust- within horizontal 24 characters, vertical 15 rows control data ment range (8 lines 24 columns mode) display format 16 16 dot mode: 15 lines 24 columns idcd14sl flag 14 16 dot mode: 17 lines 24 columns character set (font) 255 kinds (user-programmable) character pattern data character size vertical: 14 sizes (1-14 times, line units) control data horizontal: 24 sizes (1-24 times, character units) space between characters 0/2 bit (the size of one dot depends on the character size.) idccpch flag character color 16 kinds (character units) character pattern data character background color 8 kinds (character units) control data screen background color 8 kinds (set for 1 screen) idcbken flag idcbkr flag idcbkg flag idcbkb flag character rimming rim (character units) control data character pattern data reverse video, rounding (character units) character pattern data
231 m pd17068 16.2 idc display control block the idc display control block controls idc display on/off, vram, space between display characters, display format, i pin use, and the screen background color. 16.2.1 idc display control block control registers the idc display control block is controlled by idc enable register, idc mode selection register, and idc background selection register. figs. 16-2 to 16-4 show the organization and functions of each register. fig. 16-2 configuration of idc enable register caution when setting the idcen flag to 1 (at the start of display), do it while the vertical synchronizing signal is high level (vertical flyback time, v sync , is low). register flag symbol b 3 b 2 b 1 b 0 00 i d c e n 31h r/w address read/write upon reset power-on clock stop ce 00 0 1 display off display on 0 sets idc display on/off. 00 0 0 fixed to 0. idc enable register
232 m pd17068 fig. 16-3 configuration of idc mode selection register register flag symbol b 3 b 2 b 1 b 0 i d c d 1 4 s l i d c c p c h 33h r/w address read/write upon reset power-on clock stop ce 00 0 1 no space space 00 00 00 00 00 0 1 0 1 sets whether or not there is a space between display characters. v r a m s e l i d c i s e l 0 1 16 dots 14 dots sets the number of vertical dots of the display character. general-purpose i/o port i pin selects the function of the pob 2 /i pin. vram disable vram enable enables/disables the vram. idc mode selection register
233 m pd17068 fig. 16-4 configuration of idc background selection register 16.2.2 display format when the idcd14sl flag of the idc mode selection register is set (1), 14 vertical 16 horizontal dots is selected. when it is reset (0), 16 vertical 16 horizontal dots is selected. when you want to display 17 lines on one screen, select the 14 16 dots mode. 16.2.3 space between characters a 2-dot space can be set in front of a character by setting the idccpch flag of the idc mode selection register. the size of the space depends on the character size (horizontal). when a space is not set, kanji and other characters and graphics can be displayed by combining two or more characters. register flag symbol b 3 b 2 b 1 b 0 i d c b k g i d c b k b 30h r/w address read/write upon reset power-on clock stop ce 00 0 no background (black) blue 00 00 00 00 00 0 1 sets the screen background color. i d c b k e n i d c b k r do not display screen background color. display screen background color. sets whether or not screen background is displayed. 0 0 1 0 0 green 0 1 0 cyan 1 1 0 red 0 0 1 magenta 1 0 1 yellow 0 1 1 white 1 1 1 idc background selection register
234 m pd17068 fig. 16-5 space between characters l when idccpch flag is 0 l when idccpch flag is 1 2-dot space
235 m pd17068 16.2.4 screen background color the background color of the entire display screen can be set by manipulating the idc background selection register flags. the character color and screen background color can be set simultaneously. the display priority is: character color < character background color < screen background color 16.3 idc start position control block the idc start position control block can shift the display position of the entire screen by setting data in the idc start position setting register (idcorg: peripheral address 01h). 16.3.1 configuration of idc start position setting register fig. 16-6 shows the configuration of the idc start position setting register. set data when the v sync signal is low level. fig. 16-6 configuration of idc start position setting register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf0 data buffer peripheral register 8 register valid data idcorg 01h get put idc start position setting register dbf1 transfer data 0 15 (fh) x 0 15 (fh) x don't care don't care vertical start position setting vertical start position (number of scanning lines from trailing edge of vertical synchronizing signal) = 16 + 1 x (lines) horizontal start position setting horizontal start position (when idc lc oscillation is 10 mhz) = 3.2 s + 100 ns x
236 m pd17068 16.3.2 horizontal start position setting when the data set in the horizontal start position setting register is 0h and osc in = 10 mhz, the horizontal start position is set to 3.2 m s (2 characters) after the trailing edge of the horizontal synchronizing signal. each time this data is increased by 1, the horizontal start position is shifted 100 ns (1 dot of minimum size character) to the right. that is, it can be expressed as follows: horizontal start position = 3.2 m s + 100 ns (horizontal start position setting data) referring to fig. 16-7, assume that the position is a when the horizontal start position setting register set value is 0h. when the set value is made 1h, the horizontal start position moves 100 ns to the right and becomes position b. fig. 16-7 horizontal direction movement idc image area 3.2 ab after trailing edge of horizontal synchronizing signal s remarks : image area when horizontal position set data is 0h : image area when horizontal position set data is 1h
237 m pd17068 16.3.3 vertical start position setting when the data set in the vertical start position setting register is 0h, the vertical start position is set to 16 scanning lines after the trailing edge of the vertical synchronizing signal. each time this data is increased by 1, the vertical start position is moved down 1 line. this can be expressed as follows: vertical start position = 16 + 1 (vertical start position setting data) referring to fig. 16-8, assume that the vertical start position is a when the vertical start position setting register set value is 0h. when the set value is made 1h, the vertical start position is moved down 1 line to position b. fig. 16-8 vertical direction movement idc image area 16h after trailing edge of vertical synchronizing signal a b remarks : image area when vertical position setting data is 0h : image area when vertical position setting data is 1h
238 m pd17068 the display character vertical start position is determined by the vertical start position register. the vertical start position (counted by the number of horizontal scanning lines) at this time is selected as shown in fig. 16-9, according to the state of the v sync and h sync signals that are input at the v sync and h sync pins. in short, the first h sync signal after the rising edge of the v sync signal is counted as the first line. fig. 16-9 how vertical start position is counted remark # , $ , or % indicates the number of each scanning line. v sync h sync h sync a a
239 m pd17068 16.4 crom (character rom) the crom stores the idc display pattern data (character pattern data). fig. 16-10 shows the configuration of the crom. crom is allocated to crom area (3000h-4fdfh) in program memory (rom). the crom area cannot be used as normal program memory. crom is addressed with vram character pattern selection data. crom stores the data of 4080 steps (4080 24 bits: 255 characters), but since one address occupies 32 bits, its actual capacity is 8160 16 bits. (see fig. 2-2 .) fig. 16-10 configuration of crom crom address 2fffh 3000h 301fh 00h feh 4fc0h 4fdfh 16 bits 3000h 3001h crom area real address normal program memory bits 7 to 0 of character pattern selection data addressing character pattern data for one character character data rim data rim data (dummy) 301fh 301eh
240 m pd17068 16.4.1 character pattern data configuration the character pattern data is used for displaying characters and graphic patterns. one character consists of 16 horizontal dots by 16 vertical dots. since the data for 16 horizontal dots corresponds to one step of crom, the character pattern data for one character consists of 16 steps (16 24 bits). fig. 16-11 shows the configuration of the character patterns. the 8 low-order bits of the character pattern data are fixed at 1 (dummy). the character data that stores the actual display pattern consists of 8 bits. the bits corresponding to the dots that are lit are set to 1 and the bits corresponding to the dots that are not lit are set to 0. two dots of the actual display pattern correspond to one bit of character pattern data. a character pattern data is formed by dot image by superimposing 16-bit rim data (in dot units) onto the character data. if a 17k series assembler (as17k) is used, data like that shown in fig. 16-12 can be generated automatically by using a dcp pseudo instruction. a display pattern generation development tool (idc font editor) is also available. use this tool, if necessary. fig. 16-11 configuration of character data pattern examples of character pattern data are shown in fig. 16-12. in this data, 0 corresponds to n n and 1 corresponds to n . the control data specifies the character size, position, and color. b 31 b 24 b 23 b 8 b 7 b 0 character data rim data dummy (fixed to 1.)
241 m pd17068 fig. 16-12 character pattern data setting (character: n) l character pattern l setting when a dcp pseudo instruction is used real address b 31 b 24 0 h 0 0 0 0 0 0 0 0 b 23 b 16 0 0 0 0 0 1 0 0 b 15 b 8 b 7 b 0 1 h 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 2 h 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 3 h 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 4 h 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 5 h 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 6 h 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 7 h 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 8 h 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 9 h 0 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 a h 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 b h 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 c h d h 1 1 1 1 1 1 1 1 e h 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 f h 0 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 0 h 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 h 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 2 h 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 3 h 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 4 h 5 h 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 6 h 7 h 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 8 h 1 0 0 1 0 0 1 0 9 h 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 a h 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 b h 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 c h 1 0 0 1 0 0 0 1 d h 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 e h 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 f h 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 character data rim data dummy dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' dcp ' # # # o # # o # # o o # # o o o # # o o o o # # o o # # o o o o # # o # # o o o o # # o o # # o o o o # # o o # # o o o o o # # o # # o o o o o o # o o # # o o # o o o o o o # # o o #oooooo # # o o # # o o o o # # o o # # o o o o # # o o o # # o o # # o o # # o o # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' db db db db db db db db db db db db db db db db 0 4 h , 0 4 h , 0 0 h , 0 f f h 0 a h , 0 a h , 2 2 h , 0 f f h 1 1 h , 1 2 h , 2 3 h , 0 f f h 1 2 h , 2 1 h , 7 2 h , 0 f f h 1 4 h , 2 1 h , 7 2 h , 0 f f h 0 a 4 h , 1 0 h , 3 6 h , 0 f f h 0 a 4 h , 1 0 h , 3 6 h , 0 f f h 6 8 h , 1 0 h , 3 c h , 0 f f h 4 8 h , 2 0 h , 7 c h , 0 f f h 0 8 h , 2 4 h , 7 c h , 0 f f h 1 0 h , 4 c h , 5 c h , 0 f f h 1 0 h , 4 a h , 5 c h , 0 f f h 1 0 h , 9 2 h , 0 d c h , 0 f f h 2 0 h , 8 9 h , 0 c 8 h , 0 f f h 2 0 h , 9 1 h , 0 c 8 h , 0 f f h 0 c 0 h , 6 0 h , 0 0 h , 0 f f h conversion with a dcp pseudo instruction ; display_n :
242 m pd17068 16.4.2 definition of character pattern data with assembler character data can be easily defined with a 17k series assembler by using a dcp pseudo instruction. the dcp pseudo instruction description is shown below. (1) format symbol field mnemonic field operand field comment field [label:] dcp display pattern [:comment] (2) description the display pattern uses only the three characters o, #, and (blank). sixteen characters are described on one line. if a character other than these three characters is described, or if less than 16 characters are described, an error is generated. each of these three characters corresponds to one dot of the display pattern and has the following meaning: o : dot to be displayed (lit) # : rim : blank (3) assembly method before a file describing characters with a dcp pseudo instruction is assembled, it must be converted to a source file. perform this conversion as follows: # create a file defining the character using a dcp pseudo instruction. make the extension dcp. $ convert the file created at step # to a source file by executing program dcp.exe as follows: dcp.exe .dcp ( : space, .dcp: file name of created file) % when the program ends, a .asm file is created. assemble this file.
243 m pd17068 16.5 vram (video ram) 16.5.1 general fig. 16-13 shows the configuration of the vram. fig. 16-14 shows vram bank specification. the vram stores the following three kinds of data: l character pattern selection data l carriage return data (c/r) l control data 1 and 2 the vram is allocated at addresses 00h-3fh of bank 2 of data memory, and is enabled only when the vramsel flag is 1. when the vramsel flag is set to 1, neither vram nor ram exist at addresses 30h- 3fh of data memory and 0 is always read from this area. vram consists of 14 banks designated vrambank0 to vrambankd. (see fig. 4-2 .) the data at address 73h of bank 2 of data memory specifies the vram bank. one item of vram data consists of data at 3 addresses (12 bits). each bank consists of 48 nibbles. two- hundred twenty-three data items can be set as vram data. fig. 16-13 configuration of vram 0123456789abcdef vrambank0-d 0 1 2 3 4 5 6 7 fixed to 0. bank 2 specifies the vram bank. system register row address column address 01 23456789abcdef 0 1 2 row address column address 4 bits 4 bits 4 bits vram data (at 3 addresses)
244 m pd17068 fig. 16-14 vram bank specification 16.5.2 configuration of vram data fig. 16-15 shows the configuration of the vram data. one item of vram data consists of 12 bits, and is divided into an id field and a data field. fig. 16-15 configuration of vram data l id field the id field represents the state of the character pattern selection data. the id field settings and character pattern selection data states are shown in table 16-2. for details, see section 16.5.5 . table 16-2 id field settings and character pattern selection data states id field setting character pattern selection data state 0 note when combined with control data 2 0 or 1 when combined with control data 1 note becomes carriage return data only when the id field is 0 and the data field has the following value: l 10111111111 vram pointer reset c/r l 11011111111 line c/r l 11111111111 screen c/r vramsel = 0 vramsel = 1 vramsel = 1 ram (bank2) vram (bank0) ram (bank2) fixed to 0. vram (bankb) ram (bank2) fixed to 0. 73h "0000" 73h "1011" b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 h1 h2 h id data field address name
245 m pd17068 16.5.3 character pattern selection data fig. 16-16 shows the configuration of the character pattern selection data. a character pattern is data that specifies the shape and other attributes of the character displayed on a television set or other screen and is stored in the crom (character rom). bits 8 to 10 of the character pattern selection data specify the character color. bits 0 to 7 are the crom address. table 16-3 shows the correspondence between the crom address specified by the character pattern selection data and the real address. for the crom, see section 16.4 . fig. 16-16 configuration of character pattern selection data b 11 b 10 b 8 b 0 b 10 b 9 b 8 000 001 010 011 100 101 110 111 id crom address b 7 character color set the character color. black blue green cyan red magenta yellow white
246 m pd17068 table 16-3 crom address specified by character pattern selection data and real address (1/2) crom real address address 00h 3000h-301fh 01h 3020h-303fh 02h 3040h-305fh 03h 3060h-307fh 04h 3080h-309fh 05h 30a0h-30bfh 06h 30c0h-30dfh 07h 30e0h-30ffh 08h 3100h-311fh 09h 3120h-313fh 0ah 3140h-315fh 0bh 3160h-317fh 0ch 3180h-319fh 0dh 31a0h-31bfh 0eh 31c0h-31dfh 0fh 31e0h-31ffh 10h 3200h-321fh 11h 3220h-323fh 12h 3240h-325fh 13h 3260h-327fh 14h 3280h-329fh 15h 32a0h-32bfh 16h 32c0h-32dfh 17h 32e0h-32ffh 18h 3300h-331fh 19h 3320h-333fh 1ah 3340h-335fh 1bh 3360h-337fh 1ch 3380h-339fh 1dh 33a0h-33bfh 1eh 33c0h-33dfh 1fh 33e0h-33ffh crom real address address 20h 3400h-341fh 21h 3420h-343fh 22h 3440h-345fh 23h 3460h-347fh 24h 3480h-349fh 25h 34a0h-34bfh 26h 34c0h-34dfh 27h 34e0h-34ffh 28h 3500h-351fh 29h 3520h-353fh 2ah 3540h-355fh 2bh 3560h-357fh 2ch 3580h-359fh 2dh 35a0h-35bfh 2eh 35c0h-35dfh 2fh 35e0h-35ffh 30h 3600h-361fh 31h 3620h-363fh 32h 3640h-365fh 33h 3660h-367fh 34h 3680h-369fh 35h 36a0h-36bfh 36h 36c0h-36dfh 37h 36e0h-36ffh 38h 3700h-371fh 39h 3720h-373fh 3ah 3740h-375fh 3bh 3760h-377fh 3ch 3780h-379fh 3dh 37a0h-37bfh 3eh 37c0h-37dfh 3fh 37e0h-37ffh crom real address address 40h 3800h-381fh 41h 3820h-383fh 42h 3840h-385fh 43h 3860h-387fh 44h 3880h-389fh 45h 38a0h-38bfh 46h 38c0h-38dfh 47h 38e0h-38ffh 48h 3900h-391fh 49h 3920h-393fh 4ah 3940h-395fh 4bh 3960h-397fh 4ch 3980h-399fh 4dh 39a0h-39bfh 4eh 39c0h-39dfh 4fh 39e0h-39ffh 50h 3a00h-3a1fh 51h 3a20h-3a3fh 52h 3a40h-3a5fh 53h 3a60h-3a7fh 54h 3a80h-3a9fh 55h 3aa0h-3abfh 56h 3ac0h-3adfh 57h 3ae0h-3affh 58h 3b00h-3b1fh 59h 3b20h-3b3fh 5ah 3b40h-3b5fh 5bh 3b60h-3b7fh 5ch 3b80h-3b9fh 5dh 3ba0h-3bbfh 5eh 3bc0h-3bdfh 5fh 3be0h-3bffh crom real address address 60h 3c00h-3c1fh 61h 3c20h-3c3fh 62h 3c40h-3c5fh 63h 3c60h-3c7fh 64h 3c80h-3c9fh 65h 3ca0h-3cbfh 66h 3cc0h-3cdfh 67h 3ce0h-3cffh 68h 3d00h-3d1fh 69h 3d20h-3d3fh 6ah 3d40h-3d5fh 6bh 3d60h-3d7fh 6ch 3d80h-3d9fh 6dh 3da0h-3dbfh 6eh 3dc0h-3ddfh 6fh 3de0h-3dffh 70h 3e00h-3e1fh 71h 3e20h-3e3fh 72h 3e40h-3e5fh 73h 3e60h-3e7fh 74h 3e80h-3e9fh 75h 3ea0h-3ebfh 76h 3ec0h-3edfh 77h 3ee0h-3effh 78h 3f00h-3f1fh 79h 3f20h-3f3fh 7ah 3f40h-3f5fh 7bh 3f60h-3f7fh 7ch 3f80h-3f9fh 7dh 3fa0h-3fbfh 7eh 3fc0h-3fdfh 7fh 3fe0h-3fffh
247 m pd17068 table 16-3 crom address specified by character pattern selection data and real address (2/2) crom real address address 80h 4000h-401fh 81h 4020h-403fh 82h 4040h-405fh 83h 4060h-407fh 84h 4080h-409fh 85h 40a0h-40bfh 86h 40c0h-40dfh 87h 40e0h-40ffh 88h 4100h-411fh 89h 4120h-413fh 8ah 4140h-415fh 8bh 4160h-417fh 8ch 4180h-419fh 8dh 41a0h-41bfh 8eh 41c0h-41dfh 8fh 41e0h-41ffh 90h 4200h-421fh 91h 4220h-423fh 92h 4240h-425fh 93h 4260h-427fh 94h 4280h-429fh 95h 42a0h-42bfh 96h 42c0h-42dfh 97h 42e0h-42ffh 98h 4300h-431fh 99h 4320h-433fh 9ah 4340h-435fh 9bh 4360h-437fh 9ch 4380h-439fh 9dh 43a0h-43bfh 9eh 43c0h-43dfh 9fh 43e0h-43ffh crom real address address a0h 4400h-441fh a1h 4420h-443fh a2h 4440h-445fh a3h 4460h-447fh a4h 4480h-449fh a5h 44a0h-44bfh a6h 44c0h-44dfh a7h 44e0h-44ffh a8h 4500h-451fh a9h 4520h-453fh aah 4540h-455fh abh 4560h-457fh ach 4580h-459fh adh 45a0h-45bfh aeh 45c0h-45dfh afh 45e0h-45ffh b0h 4600h-461fh b1h 4620h-463fh b2h 4640h-465fh b3h 4660h-467fh b4h 4680h-469fh b5h 46a0h-46bfh b6h 46c0h-46dfh b7h 46e0h-46ffh b8h 4700h-471fh b9h 4720h-473fh bah 4740h-475fh bbh 4760h-477fh bch 4780h-479fh bdh 47a0h-47bfh beh 47c0h-47dfh bfh 47e0h-47ffh crom real address address c0h 4800h-481fh c1h 4820h-483fh c2h 4840h-485fh c3h 4860h-487fh c4h 4880h-489fh c5h 48a0h-48bfh c6h 48c0h-48dfh c7h 48e0h-48ffh c8h 4900h-491fh c9h 4920h-493fh cah 4940h-495fh cbh 4960h-497fh cch 4980h-499fh cdh 49a0h-49bfh ceh 49c0h-49dfh cfh 49e0h-49ffh d0h 4a00h-4a1fh d1h 4a20h-4a3fh d2h 4a40h-4a5fh d3h 4a60h-4a7fh d4h 4a80h-4a9fh d5h 4aa0h-4abfh d6h 4ac0h-4adfh d7h 4ae0h-4affh d8h 4b00h-4b1fh d9h 4b20h-4b3fh dah 4b40h-4b5fh dbh 4b60h-4b7fh dch 4b80h-4b9fh ddh 4ba0h-4bbfh deh 4bc0h-4bdfh dfh 4be0h-4bffh crom real address address e0h 4c00h-4c1fh e1h 4c20h-4c3fh e2h 4c40h-4c5fh e3h 4c60h-4c7fh e4h 4c80h-4c9fh e5h 4ca0h-4cbfh e6h 4cc0h-4cdfh e7h 4ce0h-4cffh e8h 4d00h-4d1fh e9h 4d20h-4d3fh eah 4d40h-4d5fh ebh 4d60h-4d7fh ech 4d80h-4d9fh edh 4da0h-4dbfh eeh 4dc0h-4ddfh efh 4de0h-4dffh f0h 4e00h-4e1fh f1h 4e20h-4e3fh f2h 4e40h-4e5fh f3h 4e60h-4e7fh f4h 4e80h-4e9fh f5h 4ea0h-4ebfh f6h 4ec0h-4edfh f7h 4ee0h-4effh f8h 4f00h-4f1fh f9h 4f20h-4f3fh fah 4f40h-4f5fh fbh 4f60h-4f7fh fch 4f80h-4f9fh fdh 4fa0h-4fbfh feh 4fc0h-4fdfh
248 m pd17068 16.5.4 carriage return data (c/r) fig. 16-17 shows the kinds of carriage return data. there are the following three kinds of carriage return data. data other than these functions as character pattern selection data. l line c/r l vram pointer reset c/r l screen c/r when displaying data exceeding the vram capacity (extended display mode) on one page, set vram pointer reset c/r data at the end of the vram. for a description of the extended display mode, see section 16.8 . fig. 16-17 kinds of carriage return data 16.5.5 control data fig. 16-18 shows the configuration of the control data. control data is used for specifying the character size, display position, and color on the character pattern screen. there are the following two kinds of control data: l control data specified at each line (control data 1) l control data specified for each character (control data 2) control data 1 is represented by 12 bits following vram address 0 (after screen c/r) and the line c/r. control data 2 is represented by 12 bits following the character data when the id field is set to 1. in short, it is used as a pair with the character pattern selection data. control data 2 modifies the character up to control data 2 directly preceding it or up to the screen c/r. specify control data 1 for each line whether or not it has changed. b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 01 10 111 111 11 01 01 111 111 11 01 11 111 111 11 screen c/r line c/r vram pointer reset c/r
249 m pd17068 # control data 1 $ control data 2 (1) functions of control data 1 # character vertical size setting (bits 8-11) table 16-4 lists the settings and corresponding character attributes. fourteen sizes (1x-14x) can be set for each line. table 16-4 vertical size setting b 11 b 8 b 7 b 4 b 3 b 0 horizontal position vertical size vertical position b 11 b 0 b 10 1 b 11 b 10 0 b 6 b 5 b 4 b 1 b 0 control data 2 character pattern selection data horizontal size rim character background color color density control data 1 b 11 b 10 b 9 b 8 0000 0001 0010 0011 1100 1101 16h 32h 48h 64h 208h 224h 8 4 2 2 1 1 size vertical width of 1 character (in interlace mode) maximum number of vertical display characters 1x 2x 3x 4x 13x 14x
250 m pd17068 $ character vertical position setting (bits 4-7) bits 4 to 7 of control data 1 set the vertical position from which display starts for each line. this setting is performed for each line. the line display position is represented by the number of dots from the last line. the set value itself becomes the line spacing. table 16-5 lists the settings and corresponding vertical positions. set the display start position of the entire screen at the idc start position setting register (idcorg). remark one dot refers to that used when the vertical size is 1x. it does not change even when the vertical size is set to a value other than 1x. table 16-5 vertical position setting % character horizontal position setting (bits 0-3) bits 0 to 3 of control data 1 set the horizontal position from which the line is to be displayed. the horizontal position is represented by the number of dots shifted relative to the horizontal start position set by the idc start position setting register (idcorg). the set value itself becomes the number of dots the position is shifted. table 16-6 lists the settings and corresponding horizontal positions. remark one dot refers to that used when the horizontal size is 1x. control data 1 b 7 b 6 b 5 b 4 0000 0001 0010 1110 1111 vertical spacing begin display 0 dots from preceding line begin display 1 dot from preceding line begin display 3 dots from preceding line begin display 14 dots from preceding line begin display 15 dots from preceding line
251 m pd17068 table 16-6 horizontal position setting (2) functions of control data 2 # character horizontal size setting (bits 6-10) table 16-7 lists the settings and corresponding character attributes. twenty-four sizes (1x-24x) can be set for each character. table 16-7 horizontal size setting remark since the horizontal size consists of 5 bits, up to 32x can be set as data. although a value exceeding this may be set, because the number of columns per line is 24, the data will not displayed correctly. control data 1 b 3 b 2 b 1 b 0 0000 0001 0010 1110 1111 begin display 0 dots from the position set by idcorg begin display 1 dot from the position set by idcorg begin display 2 dots from the position set by idcorg begin display 14 dots from the position set by idcorg begin display 15 dots from the position set by idcorg horizontal spacing control data 2 b 10 b 9 b 8 b 7 b 6 00000 00001 00010 00100 00101 00110 00111 10111 11000 1.6 s 3.2 s 4.8 s 6.4 s 8.0 s 9.6 s 11.2 s 36.8 s 38.4 s 24 12 8 6 4 4 3 1 1 size horizontal width of 1 character 1x 2x 3x 4x 5x 6x 7x 23x 24x maximum number of display characters in 1 line
252 m pd17068 $ rim setting (bit 5) bit 5 specifies rimming for the character pattern defined in crom. when it is set to 0, rimming is not executed and when it is set to 1, rimming is executed. the rim color is black only. % character background color setting (bits 1-4) table 16-8 lists the settings and corresponding background colors. the character background color is set by setting the control data of the first character of the character group to which the background color is applied. bit 4 enables/disables character background color and bits 0 to 3 set the character background color. the character background color and screen background color can be set simultaneously. table 16-8 character background color setting remark : dont care & character color density (i output) setting (bit 0) bit 0 sets the density of the character color. up to 8 character colors can be specified. however, 16 colors can be specified by accompanying the specification with the color density. the density is set by setting 1 in bit 0 of control data 2 of the first character of the character group to which the density is to be set. since the i output is also used for p0b 2 , when using it as the i pin, set the idcisel flag to 1. remark the i output is output for all the dots regardless of the character dot size. when a space is set between characters, an i signal is output at the space also. control data 2 character background color b 4 b 3 b 2 b 1 0 no background (black) 1 0 0 0 1 0 0 1 blue 1 0 1 0 green 1 0 1 1 cyan 1 1 0 0 red 1 1 0 1 magenta 1 1 1 0 yellow 1111 white
253 m pd17068 16.5.6 vram data setting example an example of vram data setting is shown in fig. 16-19. fig. 16-19 example of vram data setting remarks cont1 : control data 1 cont2 : control data 2 character : character pattern selection data line c/r : c/r that indicates the end of 1 line screen c/r : c/r that indicates the end of 1 screen 16.5.7 vram data setting cautions # when setting data at the vram, begin from address 00h of vrambank 0 in the state in which 2 is set in the bank register and the vramsel flag is set. $ vram is mapped to addresses 00h to 3fh of ram bank 2. the area beginning from address 40h is normal ram. the values at addresses 30h to 3fh are fixed to 0. therefore, do not set the vram data after address 30h. % when data is set at the vram by using index modification, the index-modified vram bank and vram row address may not be output for vram port only, but also for ports and system registers. the contents of the ports and system registers may be manipulated. (data memory is not affected.) the hardware that is affected is shown in table 16-9. therefore, when the index modification addressing is used for the addresses shown in table 16-9, write the data using a direct data memory operation instruction without using index modification (clear the ixe flag). 0123 456789 abcdef012 fixed to 0. fixed to 0. 0 2 1 3 c o n t 1 character character character character character character character character character character character character c o n t 2 c o n t 2 c o n t 2 c o n t 2 c o n t 1 control data 1 is always set at the column address after column 0 of vrambank 0 and line c/r. bcdef 0 1 2 fixed to 0. character character character character c o n t 2 c o n t 2 c o n t 1 the next control data 2 is valid for this character. 3456 f character character character fixed to 0. line c/r line c/r screen c/r vrambank 0 vrambank 1 vrambank d
254 m pd17068 table 16-9 hardware affected by index modification caution actually, there is no vram at vram addresses 30h to 3fh. do not execute an instruction that operates these addresses. when an index register increment instruction is executed, in particular, the vram addresses may become 30h to 3fh. when setting data over multiple vram banks by using an increment instruction, proceed as follows: (1) increment the vram address. when the address reaches 2fh, stop incrementing and clear the ixe flag. (2) switch the vram bank and reset the index register. (3) set the ixe flag again and start incrementing. & when the memory pointer is used to write data to the vram, ports and system registers may be operated in the same way as when index modification addressing is used. the hardware that is affected is the same as that shown in table 16-9. however, since vram addresses 30h to 3fh are not vram area, do not set them in the memory pointer. when accessing address 2fh of vram banks 1, 5, 9, and d, do not use the memory pointer, but write data with a direct memory operation instruction. ( always set control data 1 at the beginning of a line and a screen whether or not the data is to be changed. ) set the character pattern selection data sequentially from the vram low address, in the order displayed from the top left of the screen. * always set the line carriage return data at the end of a line. + always set the vram pointer reset carriage return data at the end of the vram data when data exceeding the vram capacity (extended display mode) is displayed by program. , always set the screen carriage return data at the end of the data of a screen. - when displaying data in the extended display mode, before reading the vram pointer reset carriage return data, rewrite the vram data at the first line that exceeds the vram capacity. vram address after affected hardware index modification vram bank vram address bank address hardware name 1, 5, 9, d 2fh 2 6fh port 2d 30h to 32h 2 70h to 72h ports 2a-2c 33h 2 73h vram bank specification 34h to 3fh 74h to 7fh system registers 3, 7, b 34h to 3fh 74h to 7fh system registers
255 m pd17068 16.6 vram pointer 16.6.1 configuration of vram pointer fig. 16-20 shows the configuration of the vram pointer. the vram pointer generates an interrupt request at the specified vram address. fig. 16-20 configuration of vram pointer dbf vram pointer buffer (idcvp) 10-bit counter vram pointer register (idcvpr) dbf reset increment signal v sync line end signal increment clock c/r detection match detection interrupt request
256 m pd17068 16.6.2 vram pointer buffer (idcvp) fig. 16-21 shows the configuration of the vram pointer buffer. the vram buffer outputs the vram pointer value. since the vram addresses at which the data has been already used for display can be identified by reading the vram pointer value, the vram data before the read address can be rewritten. fig. 16-21 configuration of vram pointer buffer remark b n : vram bank r n : vram row address c n : vram column address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf0 data buffer peripheral register 10 name get vram pointer buffer dbf1 valid data transfer data b 8 b 9 idcvp 42h m s b l s b b 1 b 0 r 1 r 0 c 3 c 2 c 1 c 0 b 2 b 3 m s b l s b 000 0 00
257 m pd17068 16.6.3 vram pointer register (idcvpr) fig. 16-22 shows the configuration of the vram pointer register. the vram pointer register specifies the vram address at which an interrupt is to be generated. when the value set in the vram pointer register and the value of the vram pointer match, an interrupt request is issued. therefore, vram data before the vram address set in the vram pointer register is rewritten in the interrupt routine. fig. 16-22 configuration of vram pointer register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf0 data buffer peripheral register 16 register get dbf1 transfer data b 8 b 9 idcvpr 43h b 10 b 11 b 12 b 13 b 14 b 15 0 0 0 0 0 0 vram pointer register put sets the address at which an interrupt is to be generated, which is compared with the vram pointer valid data
258 m pd17068 16.7 idc output pins (blank, red, green, blue, i pins) 16.7.1 functions of idc output pins the idc output pins (blank, red, green, blue, i pins) are cmos push-pull output pins and output an active high signal. the signal that blanks the broadcast image (blanking signal) is output from the blank pin and the character pattern signal (or of r, g, b signals) is output from the red, green, blue, and i pins. 16.7.2 idc output waveforms fig. 16-23 shows the idc output signal waveforms. when there is no rim, the blanking signal and character pattern signal output the same signal. when there is a rim, the blanking signal enveloping the character pattern signal is output from the blank pin. when the least significant bit of control data 1 is 1, the character pattern signal output from the i pin outputs high level for the display character only. fig. 16-23 idc output waveforms (1 character) (a) when there is no rim (b) when there is a rim (c) i pin output character pattern signal blanking signal character pattern signal blanking signal 1 character red, green, blue pins i pin
259 m pd17068 16.8 sample program 16.8.1 displaying data exceeding vram capacity (extended display mode) data exceeding the vram capacity can be displayed by applying an interrupt and rewriting the data that has already been displayed by program while vram data is being displayed on the screen. when displaying data in the extended display mode, set the vram pointer reset c/r at the end of the vram data. normal screen display can be performed even when the character group to be displayed exceeds 8 lines as long as the vram data does not exceed the vram capacity. (1) example of normal screen display exceeding 8 lines 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ch 0 8 00 :00 line 0 1 2 3 4 5 6 7 8 9 line 10 column column p n r g g r e o in off l low sof low r e t off p peak bass ba l rebl ctur hu e se te e r i p n o i h i h a h s e r g n p h h d
260 m pd17068 (2) example in extended display mode when displaying a screen like the one shown below, use the extended display mode. the extended display mode flowchart is shown on the next page. 01234567 91011121314151617 line 0 1 2 3 4 5 6 7 8 9 10 18 19 20 21 22 11 12 13 14 15 line 16 column column 8 0 1234567 9abcdefghi jklm 8 0 1 2 3 4 5 6 7 8 9 a b c d e f 12345 6 7 9 abcdefghi j k lm 8 0 2 34 5 6 7 9 abcdefghi jk l m 8 1 0 3 4567 9 abcdefghi jklm 8 2 1 0 4 567 9abcdefgh i jklm 8 3 2 1 0 567 9abcdefgh i jklm 8 4 3 2 1 0 6 79abcdefghijklm 8 5 4 3 2 1 0 7 9a bcdefg h i j k lm 8 6 5 4 3 2 1 0 9abcdefgh i j k lm 8 7 6 5 4 3 2 1 0 9 abcde fghi j klm 8 7 6 5 4 3 2 1 0 a bc de fgh i j k lm 9 8 7 6 5 4 3 2 1 0 bcde fgh i j k lm a 9 8 7 6 5 4 3 2 1 0 cdefgh i j klm b a 9 8 7 6 5 4 3 2 1 0 de fg hi jk lm c b a 9 8 7 6 5 4 3 2 1 0 efgh i j klm d c b a 9 8 7 6 5 4 3 2 1 0 fgh i j klm e d c b a 9 8 7 6 5 4 3 2 1 0 g hi j k lm
261 m pd17068 (3) flowchart the flowchart when one display data is displayed by rewriting the vram data once is shown below. start initialization defines the disp flag ("1" at second data display) as the flag that indicates if the idc display uses the 1st vram data or 2nd vram data. initializes the ram, etc. clears the disp flag. sets the vram pointer reset c/r at the end of the vram data. sets the 2nd data write timing. must be set at least before the vram pointer reset c/r is read. sets the screen c/r at the end of the vram data. the interrupt timing must be before the end of display of the 2nd data. sets the disp flag. set 1st vram data set vram address at which interrupt request is to be issued, in idcvpr end starts idc display. checks if the v sync signal is low level and sets the idcen flag. interrupt routine disp = 1 ? yes no interrupt enable idcen ? 1 write 2nd vram data from vram top address set vram address at which interrupt request is to be issued, in idcvpr set1 disp interrupt enable reti rewrite vram rewritten by 2nd vram data at 1st vram data sets the vram pointer reset c/r at the end of the vram data. set vram address at which interrupt request is to be issued, in idcvpr clr1 disp interrupt enable reti the interrupt timing must be before the end of display of the 2nd data. clears the disp flag.
262 m pd17068 17. horizontal synchronizing signal counter 17.1 general fig. 17-1 outlines the horizontal synchronizing signal counter. the horizontal synchronizing signal counter counts the horizontal synchronizing signal (h sync signal) separated from the image signal sent from the broadcast station. it is counted up at the rising edge of the synchronizing signal. the frequency of the horizontal synchronizing signal can be found, and used to detect which broadcast station is using the frequency currently being received, by dividing the count value by the gate open time (set by h sync counter gate control register). fig. 17-1 horizontal synchronizing signal counter remarks 1. hscgostt (bit 3 of h sync counter gate register: see fig. 17-4 ): detects opening and closing of the h sync counter gate. 2. hscgt1 and hscgt0 (bits 1 and 0 of the h sync counter gate control register: see fig. 17-3 ) : control opening and closing and the open time of the h sync counter gate. 17.2 gate input amplifier fig. 17-2 shows the configuration of the gate input amplifier. the gate input amplifier is the self-bias type. to prevent erroneous operation by noise, use it without a coupling capacitor. input the signal at a full amplitude of low level 0.2v dd or less and high level 0.8v dd or more. fig. 17-2 gate input amplifier p0b 3 /hscnt gate input amplifier on/off 1.69 ms hscgt1 flag hscgt0 flag hscgostt flag h sync counter (6 bits) dbf h sync counter data register (hsc) gate clock generator p0b 3 /hscnt to gate
263 m pd17068 17.3 gate control the h sync counter gate is controlled by the hscgt flag of the h sync counter gate control register and the hscgostt flag of the h sync counter gate judge register. figs. 17-3 and 17-4 show the organization and functions of the h sync counter gate control register and h sync counter gate judge register. the horizontal synchronizing signal counter input pin (hscnt pin) is also used for p0b 3 . when using p0b 3 as the hscnt pin, set it to the input mode. if p0b 3 is used as the hscnt pin, when it is read, 0 is always read. when using p0b 3 as a port, set the h sync counter gate control register to all 0. fig. 17-3 configuration of h sync counter gate control register register flag symbol b 3 b 2 b 1 b 0 h s c g t 1 h s c g t 0 11h r/w address read/write 0 upon reset power-on clock stop ce 00 0 01 10 11 gate closed mode gate open mode 1.69 ms gate open mode not to be set. 00 00 00 controls the h sync counter gate. 00 fixed to 0. h sync counter gate control register
264 m pd17068 fig. 17-4 configuration of h sync counter gate judge register 17.3.1 h sync counter gate mode selection flag (hscgt ) the hscgt flag controls the h sync counter input gate clock. the following three modes can be selected: (a) gate closed mode the gate clock generator does not operate and the gate remains closed. therefore, the h sync counter does not operate. self-biasing of the input pin is also disabled. when using hscnt/p0b 3 as a port, always select this mode. (b) gate open mode after the gate is opened and the h sync counter is reset, counting of the h sync signal begins. the input pin is biased. (c) 1.69 ms gate open mode counting of the h sync signal begins after a maximum delay of 8 ms after the gate is opened and the h sync counter is reset. the gate clock generator operates and the gate time becomes 1.69 ms. the input pin is biased. 17.3.2 h sync counter gate open status flag (hscgostt) the hscgostt flag detects the status of the h sync counter gate. it is normally set (1) while the gate is open. in the 1.69 ms gate open mode, 1 is read from hscgostt from the time the data was set even if a gate clock does not arrive. register flag symbol b 3 b 2 b 1 b 0 h s c g o s t t 12h r address read/write upon reset power-on clock stop ce 00 0 1 detects opening and closing of the h sync counter gate. gate closed gate open 00 0 fixed to 0. h sync counter gate judge register 00
265 m pd17068 17.4 h sync counter data register (hsc) fig. 17-5 shows the configuration of the h sync counter data register. fig. 17-5 configuration of h sync counter data register 17.5 sample program a sample program for the horizontal synchronizing signal counter is shown below. example 1.69 ms gate open mode initflg hscgt1, not hscgt0 ; sets the h sync counter to the 1.69 ms gate ; open mode. loop : slf1 hscgostt ; detects the hscgostt flag. br loop ; and if the hscgostt flag is 0, reads the count ; value at the data buffer. get dbf, hsc ; 17.6 state at reset at power-on reset, clock-stop, and ce reset, the gate is set to the gate closed mode and the h sync counter is reset. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral register dbf3 dbf2 dbf0 data buffer peripheral register 8 register valid data hsc 04h get dbf1 transfer data 0 3fh (63) x hold hold h sync counter data register number of horizontal synchronizing signals h sync counter count value read
266 m pd17068 18. pll frequency synthesizer the pll (phase locked loop) frequency synthesizer is used to lock vhf (very high frequency) band frequencies to a fixed frequency using a phase error comparison system. 18.1 general fig. 18-1 outlines the pll frequency synthesizer. a pll frequency synthesizer can be built by connecting a low pass filter (lpf), voltage controlled oscillator (vco), and prescaler externally. the pll frequency synthesizer divides the signal input from the vco using a programmable divider and outputs the phase error with the reference frequency to the eo pin. the pll frequency synthesizer operates only when the ce pin is high level. when the ce pin is low level, the pll frequency synthesizer is disabled. for a description of the pll disabled state, see section 18.5. fig. 18-1 pll frequency synthesizer remarks 1. pllrfck3 to pllrfck0 (bits 0-3 of pll reference clock selection register: see fig. 18-5 ): set the pll frequency synthesizer reference frequency f r . 2. plulsen1 and plulsen0 (bits 1 and 0 of pll unlock flip-flop sensibility selection register: see fig. 18-9 ): set the unlock flip-flop set delay time. 3. pllul (bit 0 of pll unlock flip-flop judge register: see fig. 18-8 ): detects the state of the unlock flip-flop. note external circuit. psc dbf 1/16, 1/17 1/8 vco 8 mhz programmable divider (pd) charge pump eo low pass filter (lpf) pllrfck3 flag pllrfck2 flag pllrfck1 flag pllrfck0 flag plulsen1 flag plulsen0 flag pllul flag phase compa- rator ( -det) prescaler ( pb595) note reference frequency generator unlock detection block note note voltage controlled oscillator (vco)
267 m pd17068 18.2 programmable divider 18.2.1 configuration fig. 18-2 shows the configuration of the programmable divider. the programmable divider divides the signal input from the vco pin at the division ratio set by program. the division method is the pulse swallow method. the division value is set by the pll data register through a data buffer. fig. 18-2 programmable divider dbf 16 pll data register 12 bits 4 bits 12 4 pll disable signal vco psc programmable counter (12 bits) to -det swallow counter (4 bits) f n
268 m pd17068 18.2.2 programmable divider and pll data register the division value is set in the swallow counter and programmable counter by the pll data register through a data buffer. the swallow counter and programmable counter are 4-bit and 12-bit binary down counters, respectively. data is written to the pll data register with the put pllr, dbf instruction, and read from the pll data register with the get dbf, pllr instruction. for a description of the division value (n value) setting method, see section 18.6. (1) pll data register and data buffer fig. 18-3 shows the relationship between the pll data register and the data buffer. all 16 bits of the pll data register are valid. the 12 high-order bits are set in the programmable counter and the 4 low-order bits are set in the swallow counter. fig. 18-3 pll data register and data buffer b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 symbol peripheral address dbf3 dbf2 dbf0 data buffer peripheral register 16 register get dbf1 transfer data b 8 b 9 pllr 41h b 10 b 11 b 12 b 13 b 14 b 15 pll data register put valid data 0 255 (00ffh) 256 (0100h) x 2 16 - 1 (ffffh) division ratio n: n=x sets the division ratio used for the pll frequency synthesizer. not to be set.
269 m pd17068 (2) relationship between programmable divider division value n and divided output frequency the relationship between the value n set in the pll data register and the frequency f n of the signal divided and output by the programmable divider, is shown below. for details, see section 18.6. f n = f in (f in : input frequency) n 18.3 reference frequency generator fig. 18-4 shows the configuration of the reference frequency generator. the reference frequency generator generates the pll frequency synthesizer reference frequency f r by dividing the 8-mhz signal of a crystal oscillator. the reference frequency can be selected from among 5 khz, 6.25 khz, 10 khz, 12.5 khz, and 25 khz. the reference frequency is selected with the pllrfck flags of the pll reference clock selection register. fig. 18-5 shows the organization and functions of the pll reference clock selection register. fig. 18-4 reference frequency generator 8 mhz pllrfck3 flag pllrfck2 flag pllrfck1 flag pllrfck0 flag mux off 5 khz 6.25 khz 10 khz 12.5 khz 25 khz frequency divider pll disable signal to -det
270 m pd17068 fig. 18-5 configuration of pll reference clock selection register remark if pll disabled is selected, the vco pin is pulled down internally. the eo pin is floated. register flag symbol b 3 b 2 b 1 b 0 p l l r f c k 3 13h r/w address read/write 11 10 khz 6.25 khz 12.5 khz 11 pll reference clock selection register p l l r f c k 2 p l l r f c k 1 p l l r f c k 0 upon reset power-on clock stop ce 11 11 01 10 01 01 01 00 00 11 0 0 1 0 5 khz sets the pll frequency synthesizer reference frequency f r . 25 khz pll disabled not to be set. others 11 11 hold
271 m pd17068 18.4 phase comparator ( f -det), charge pump and unlock detection block 18.4.1 configuration of phase comparator, charge pump and unlock detection block fig. 18-6 shows the configuration of the phase comparator, charge pump and unlock detection block. the phase comparator ( f -det) compares the phase of the divided frequency (f n ) signal output from the programmable divider and that of the reference frequency (f r ) signal output from the reference frequency generator and outputs an up request signal (up) or down request signal (dw). the charge pump outputs the output of the phase comparator from the error out pin (eo pin). the unlock detection block consists of a delay control circuit and an unlock flip-flop, and detects the pll frequency synthesizer unlocked state. sections 18.4.2 to 18.4.4 describe the operation of the phase comparator, charge pump, and unlock detection block. fig. 18-6 phase comparator, charge pump and unlock detection block 18.4.2 phase comparator functions as shown in fig. 18-6, the phase comparator compares the phase of the programmable divider divided (f n ) output and that of the reference frequency (f r ) signal and outputs an up request signal or down request signal. that is, if divided frequency f n is lower than reference frequency f r , an up request signal is output, and if divided frequency f n is higher than reference signal f r , a down request signal is output. fig. 18-7 shows the relationship among the reference frequency f r , division frequency f n , up request signal, and down request signal. in the pll disabled state, neither an up request signal nor a down request signal is output. the up request and down request signals are input to the charge pump and unlock detection block. f r f n up dw plulsen1 flag plulsen0 flag pllul flag unlock flip-flop charge pump eo pll disable signal programmable divider delay control circuit reference frequency generator phase comparator ( -det) unlock detection block
272 m pd17068 fig. 18-7 f r , f n , up, and dw signal relationship (a) when f n phase lags f r phase (b) when f n phase leads f r phase (c) when f n and f r are same phase (d) when f n frequency lower than f r frequency 18.4.3 charge pump as shown in fig. 18-6, the charge pump outputs the up request signal or down request signal sent from the phase comparator, from the error out pin (eo pin). error output pin output, division frequency f n , and reference frequency f r have the following relation: when reference frequency f r > division frequency f n : low level output when reference frequency f r < division frequency f n : high level output when reference frequency f r = division frequency f n : floating f r f n up dw f r f n up dw f r f n up dw f r f n up dw
273 m pd17068 18.4.4 configuration and functions of unlock detection block as shown in fig. 18-6, the unlock detection block detects the pll frequency synthesizer unlocked state from the phase comparator up request and down request signals. that is, since the up request signal or down request signal outputs low level while the pll frequency synthesizer is in the unlocked state, the unlocked state can be detected by monitoring this low level signal. when the pll frequency synthesizer is in the unlocked state, the unlock flip-flop is set (1). the state of the unlock flip-flop is detected by the pllul flag of pll unlock flip-flop judge register. the unlock flip-flop is set at the period of the reference frequency f r selected at the time. the contents of the pll unlock flip-flop judge register are read (peek instruction) and reset (read & reset). the unlock flip-flop must be detected at a period longer than reference frequency f r period 1/f r . the delay control circuit controls the state that sets the unlock flip-flop by applying a delay to the phase comparator up request signal and down request signal. in other words, if the delay is long, the unlock flip- flop is not set even if the phase deviation between the division frequency (f n ) and reference frequency (f r ) signals is large. the delay control circuit delay time is set with the pll unlock flip-flop sensibility selection register. 18.4.5 organization and functions of pll unlock flip-flop judge register fig. 18-8 shows the organization and functions of the pll unlock flip-flop judge register. this register is a read only register, and is reset when the data is read and set to the window register using the peek instruction. since the unlock flip-flop is set at the period of reference frequency f r , the pll unlock flip-flop judge register must be read at the window register at a slower period than reference frequency period 1/f r . fig. 18-8 configuration of pll unlock flip-flop judge register register flag symbol b 3 b 2 b 1 b 0 p l l u l 22h r & reset address read/write upon reset power-on clock stop ce 00 0 1 detects the state of the unlock flip-flop. unlock flip-flop = 0 : pll locked unlock flip-flop = 1 : pll unlocked 0 * 0 fixed to 0. pll unlock flip-flop judge register 0 0 * undefined hold hold
274 m pd17068 18.4.6 organization and functions of pll unlock flip-flop sensibility selection register fig. 18-9 shows the organization and functions of the pll unlock flip-flop sensibility selection register. when the unlock flip-flop disable state is set by the pll unlock flip-flop sensibility selection register, the state of the unlock flip-flop is undefined. fig. 18-9 configuration of pll unlock flip-flop sensibility selection register 18.5 pll disabled state the pll frequency synthesizer is disabled while the ce pin is low level. the pll frequency synthesizer is also disabled when pll disabled is selected by the pll reference clock selection register. table 18-1 shows the state of each block at pll disabled. since the pll reference clock selection register is not initialized (previous state is held) at ce reset, it is reset to its previous state when the ce pin rises to high level after dropping to low level and pll disabled is set. therefore, when pll disabled must be set at ce reset, the pll reference clock selection register must be initialized by program. at power-on reset, pll disabled is set. register flag symbol b 3 b 2 b 1 b 0 p l u l s e n 1 p l u l s e n 0 32h r/w address read/write 0 upon reset power-on clock stop ce 00 0 01 10 11 1.25-1.5 s or more 3.5-37.5 s or more 0.25-0.5 s or more unlock flip-flop disabled 00 00 hold sets the delay time between the reference (f r ) and division frequency (f n ) signals, which is necessary to set the unlock flip-flop. 00 fixed to 0. pll unlock flip-flop sensibility selection register hold
275 m pd17068 table 18-1 state of each block at pll disabled 18.6 pll frequency synthesizer use to control the pll frequency synthesizer, the following data is necessary: (1) reference frequency: f r (2) division value: n the pll data setting method is shown below. (1) reference frequency f r setting the reference frequency is set by the pll reference clock selection register. (2) division value n computation method division value n is computed as follows: n = f vco : vco pin input frequency f r : reference frequency p : prescaler division ratio (3) pll data setting example the method of setting the data to receive a vhf band broadcast station is shown below. a m pb595 is used as the prescaler. computation is carried out with the fixed division ratio p of 8. receiving frequency : 55.25 mhz reference frequency : 5 khz intermediate frequency : 45.75 mhz block state condition reference frequency generator output stopped when pllrfck = 1111b. output not stopped. ce pin = low level programmable counter frequency division stopped when pllrfck = 1111b (pll disabled) or ce pin = phase comparator output stopped charge pump error output pin floated vco pin pulled down internally psc pin low level output low level. f vco p f r
276 m pd17068 division value n is: n = = = 2525 (decimal) = 09ddh (hexadecimal) data is written to the pll data register and pll reference clock selection register as follows: 18.7 sample program a sample program for controlling the pll frequency synthesizer is shown below. example mov wr, #00 b ; sets the unlock flip-flop set signal delay time. poke plllock, wr ; mov wr, #10 b ; sets the reference frequency. poke pllrf, wr bank0 mov dbf3, # b ; sets the division value in dbf (bit 0 of dbf0 is the lsb). mov dbf2, # b; mov dbf1, # b; mov dbf0, # b; put pllr, dbf ; sets the division value into the swallow counter and programmable counter. ul : ; n steps or more (f r period or more) note 1 skf1 pllul br ul mov wr, #0010b ; sets the unlock flip-flop set signal delay time. note 2 poke plllock, wr notes 1. read the unlock flip-flop at an interval greater than the reference frequency period. if the interval is shorter than this, the unlock flip-flop may not be read correctly, depending on the timing. 2. the first delay time is made maximum and pll is locked loosely. next, the delay time is made minimum and the pll is locked fully. when this is done, viewed overall, the time until the pll is locked can be shortened and the pll locking precision can be raised. f vco 55250 + 45750 p f r 8 5 pllr 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 09 dd 0 0 1 0 5 khz pllrf .......................
277 m pd17068 18.8 state at reset 18.8.1 at power-on reset since the pll reference clock selection register is initialized to 1111b, the pll disabled state is set. 18.8.2 at clock-stop the pll disabled state is set at the time the ce pin drops to low level. 18.8.3 at ce reset (1) ce reset caused by clock stop since clock-stop initializes the pll reference clock selection register to 1111b, the pll disabled state is set. (2) ce reset when clock not stopped since the pll reference clock selection register retains its previous state, the previous state is set when the ce pin rises to high level. 18.8.4 during the halt state if the ce pin is high level, the set state is held.
278 m pd17068 19. standby the standby function is used to reduce the supply current during back-up. 19.1 standby functions fig. 19-1 outlines the standby block. the standby block reduces the device current drain by stopping some, or all, operations of the device. the standby block has the following three functions. these functions can be used to suit the application. # halt function $ clock-stop function % device operation control by ce pin the halt function reduces the device current drain by stopping cpu operation with a halt h instruction. the clock-stop function reduces the device current drain by stopping the oscillation circuit with a stop s instruction. since the ce pin is used to control operation of the image display controller (idc) and pll frequency synthesizer and to reset the device, its operation control function is said to be a standby function.
279 m pd17068 fig. 19-1 standby block remarks 1. rlsen (bit 0 of clock-stop release enable register: see fig. 20-5 ): releases clock-stop. 2. p1b2edet (bit 0 of p1b 2 pin edge detection register: see fig. 19-6 ): detects the rising edge input of the p1b 2 pin. 3. ce (bit 0 of ce pin level judge register: see fig. 19-8 ): detects the status of the ce pin. 4. ceedet (bit 0 of ce pin edge detection register: see fig. 19-9 ): detects the rising edge input of the ce pin. halt block btm0cy input latch p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out cpu program counter instruction decoder alu system register control register clock stop block rlsen flag p1b2edet flag ce flag ceedet flag p1b 2 /rls stp ce x out x in internal clock interrupt control block halt control circuit (halt h) clock-stop control circuit (stop s)
280 m pd17068 19.2 halt function 19.2.1 general the halt function stops the cpu clock by executing a halt h instruction. when a halt h instruction is executed, the program halts and remains stopped until the halt state is released. in the halt state, the device current drain is reduced by the amount of the cpu operating current. the halt state is released by key input, basic timer 0 and interrupt. the release conditions are specified with the h operand of the halt h instruction. the halt h instruction is valid regardless of the ce pin input level. 19.2.2 halt state in the halt state, all operations of the cpu are stopped. that is, the halt h instruction stops program execution. however, the peripheral hardware remains in the state set before the halt h is executed. for an operation description of each hardware device, see section 19.4. 19.2.3 halt release conditions fig. 19-2 shows the halt release conditions. the halt release conditions are set with the 4-bit data specified by the h operand of the halt h instruction. the halt state is released when the condition set to 1 at the h operand is satisfied. when the halt state is released, the program is executed from the instruction after the halt h instruction. when multiple release conditions are set, the halt state is released if even one of the set conditions is satisfied. when reset (power-on reset or ce reset) is applied to the device, the halt state is released and the reset operations are performed. when 0000b is set at halt release condition h, no halt condition is set. if reset (power-on reset or ce reset) is applied to the device at this time, the halt state is released. fig. 19-2 halt release conditions operand b 3 b 2 b 1 b 0 sets the halt state release conditions. release when a high-level signal is input to port 0d. release when the carry flip-flop for the basic timer 0 is set (1). undefined (fix it to "0".) release when an interrupt is accepted. halt h (4 bits) 0 : do not release halt state even if condition satisfied. 1 : release halt state when condition satisfied.
281 m pd17068 19.2.4 halt release by key input halt release by key input is set by halt 0001b instruction. when the halt release by key input is set, the halt state is released when high level is input at any one of the 0d port lines (p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in and p0d 0 /adc 1 /xt out pins) each 0d port pin has a built-in pull-down resistor. (1) when general-purpose output port is made key source execute a halt 0001b instruction after the key source signal general-purpose output port is made high level. note that if an alternate switch like switch a in the figure above is used, while switch a is closed, high level is applied to the p0d 0 /adc 1 /xt out pin and the halt state is immediately released. (2) when p0d 0 /adc 1 /xt out , p0d 1 /adc 2 /xt in , p0d 2 /adc 3 , or p0d 3 /adc 4 pin used as a/d converter input avoid using the following method as much as possible. when the p0d 0 /adc 1 /xt out , p0d 1 /adc 2 /xt in , p0d 2 /adc 3 , or p0d 3 /adc 4 pin is selected as an a/d converter input, the selected pin (only one pin can be selected at one time) is disconnected from the input latch and connected to the internal a/d converter. if high level is unexpectedly input to the pin when it is selected as the a/d converter input, the latch circuit is held at high level. if a halt 0001b instruction is executed in this state, the halt state is immediately released even when an instruction to make the input latch high level is executed because the latch has already been high level. p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out general-purpose output port latch switch a p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out general-purpose output port latch a/d input a/d input
282 m pd17068 (3) when used by connecting watchdog timer oscillator to p0d 0 /adc 1 /xt out or p0d 1 /adc 2 /xt in pin avoid the using the following method as much as possible. when the p0d 0 /adc 1 /xt out or p0d 1 /adc 2 /xt in pin is selected as the watchdog timer oscillator connection pin, it is disconnected from the input latch and connected to the internal watchdog timer. if high level is unexpectedly input to the pin when it is selected as the watchdog timer oscillator connection pin, the latch circuit is held at high level. when a halt 0001b instruction is executed in this state, the halt state is immediately released even if an instruction to make the input latch high level is executed because the latch has already been high level. (4) when halt released by other microcomputer, etc. the p0d 0 /adc 1 /xt out , p0d 1 /adc 2 /xt in , p0d 2 /adc 3 , and p0d 3 /adc 4 pins can be used as general-purpose input pins with pull-down resistors. halt can be released by another microcomputer, etc. as shown in the figure above. p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out general-purpose output port latch watchdog timer p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out general-purpose output port latch output port microcomputer, etc.
283 m pd17068 19.2.5 halt release by basic timer 0 halt release by basic timer 0 is set by the halt 0010b instruction. when halt release by basic timer 0 is set, the halt state is released simultaneously with setting (1) of the carry flip-flop of basic timer 0. the carry flip-flop of basic timer 0 corresponds to the btm0cy flag, and is set at a fixed cycle (1 ms, 5 ms or 100 ms). the halt state can be released at a fixed cycle. example program that releases the halt state every 100 ms and executes process a every second. m1 mem 0.10h ; 1 second counter hlttmr dat 0010b ; symbol definition clr2 btmck1, btmck0 ; built-in macro ; sets the cycle of the carry flip-flop of basic timer ; 0 to 100 ms. loop : halt hlttmr ; sets the condition of release caused by the carry ; flip-flop of basic timer 0 and sets to the halt ; state. skt1 btm0cy ; built-in macro br loop ; if btm0cy flag is not set, branches to loop. add m1, #0100b ; adds 0100b to contents of m1. skt1 cy ; built-in macro br loop ; if a carry is generated, executes process a. process a br loop 19.2.6 halt release by interrupt halt release by interrupt is set by the halt 1000b instruction. when halt release by interrupt is set, the halt state is released simultaneously with acceptance of an interrupt. as described in chapter 11 , there are 10 interrupt sources. therefore, which interrupt source releases the halt state must be specified by the program beforehand. to accept an interrupt, enable all interrupts (ei instruction) and enable each interrupt (interrupt enable flag set) must be satisfied, in addition to issuing an interrupt request from each interrupt source. even if an inter- rupt request is issued, if that interrupt is not enabled, the interrupt is not accepted and the halt state is not released. if the halt state is released by acceptance of an interrupt, the program flow branches to the vector address of the interrupt. if an reti instruction is executed after interrupt handling, the program flow returns to the instruction after the halt instruction.
284 m pd17068 example hltint dat 1000b ; halt condition symbol definition intbtm2 dat 0006h ; interrupt vector address symbol definition int0pin dat 000ah ; interrupt vector address symbol definition start : ; program address 0000h br main org intbtm2 ; basic timer 2 interrupt vector address (0006h) br inttimer org int0pin ; int 0 pin interrupt vector address (000ah) process a ; int 0 pin interrupt handling br ei_reti inttimer : process b ; basic timer 2 interrupt handling ei_reti : ei reti main : set2 ipbtm2, ip0 ; built-in macro initflg not btm2exck, not btm2zx, btm2ck1, not btm2ck0 ; built-in macro ; sets basic timer 2 interrupt time interval to 1 ms. loop : process c ; main routine processing ei ; enable all interrupts. halt hltint ; sets halt release by interrupt. ; # br loop in the example above, when a basic timer 2 interrupt is accepted, the halt state is released and process b is executed. when an int 0 pin interrupt is accepted, process a is executed. each time the halt state is released, process c is executed. when an int 0 pin interrupt request and a basic timer 2 interrupt request are issued at the same time in the halt state, process a is executed because the int 0 pin request has higher priority over the basic timer 2 request. when an reti instruction is executed after process a is executed, the program flow returns to the br loop instruction of # , but the br loop instruction is not executed and the basic timer 2 interrupt is accepted. when a reti instruction is executed after execution of basic timer 2 interrupt handling process b, the br loop instruction is executed.
285 m pd17068 caution specify a nop instruction, immediately before a halt instruction which is released when an interrupt request flag (irq ) with the corresponding interrupt enable flag (ip ) set, is set. a nop instruction specified immediately before a halt instruction generates one-instruction execution time between the irq manipulation instruction and halt instruction. in example 1, clearing irq by executing the clr1 irq instruction affects the halt instruction correctly. in example 2, however, the clr1 irq instruction does not affect the halt instruction and the system does not enter the halt mode, because a nop instruction is not placed immediately before the halt instruction. example 1. program which correctly executes the halt instruction ; sets irq . clr1 irq nop ; places a nop instruction before the halt instruction. ; (clearing irq correctly affects the halt instruction.) halt 1000b ; executes the halt instruction correctly (enters the halt ; mode). 2. program which does not correctly execute the halt instruction ; sets irq . clr1 irq ; clearing irq does not affect the halt instruction. ; (it affects the instruction after the halt instruction.) halt 1000b ; ignores the halt instruction (does not enter the halt ; mode).
286 m pd17068 19.2.7 when multiple release conditions set simultaneously when multiple halt release conditions are set, the halt state is released if even one of the set release conditions is satisfied. the following example indicates how to judge multiple release conditions when they are satisfied. example 1 hltint dat 1000b hlttmr dat 0010b hltkey dat 0001b int0pin dat 000ah ; int 0 interrupt vector address symbol definition start : br main org int0pin process a ; int 0 interrupt handling ei reti tmrup : ; timer carry processing process b ret keydec : ; key input processing process c ret main : set1 p0c0 ; sets key source output data (high level) at key ; source pin (p0c 0 ). set2 btmck1, btmck0 ; built-in macro ; sets the cycle of the carry flip-flop of the basic ; timer 0 to 1 ms. set1 ip0 ; built-in macro ; enables int 0 pin interrupt. ei loop : halt hltint or hlttmr or hltkey ; sets halt release conditions to interrupt, basic ; timer 0 carry, and key input. skf1 btm0cy ; built-in macro ; detects btm0cy flag. call tmrup ; if set (1), executes basic timer 0 carry processing. call keydec ; if latched, executes key input processing. (how- ; ever, if the interrupt handling and timer process- ; ing periods are long, key scanning must be ; repeated.) br loop
287 m pd17068 19.3 clock-stop function the clock-stop function stops the 8 mhz crystal oscillation circuit (clock stopped state) by executing a stop s instruction. the supply current is reduced by up to 15 m a. specify 0000b at operand s of the stop s instruction. the stop s instruction is valid only when the ce pin is low level. if a stop s instruction is executed while the ce pin is high level, it is executed as a nop instruction. always execute a stop s instruction when the ce pin is low level. the clock-stop state is released by raising the ce pin from low level to high level (ce reset). 19.3.1 clock-stop state since the crystal oscillation circuit is stopped in the clock-stop state, operation of the cpu, peripheral hardware, and other devices is stopped. for a description of operation of the cpu and each item of peripheral hardware, see section 19.4. in the clock-stop state, the power failure detection circuit does not operate even if the power supply voltage v dd drops to 2.2 v. data memory can be backed up with a low voltage. for a description of the power failure detection circuit, see section 20. 19.3.2 clock-stop state release the clock-stop state can be released with the three methods described below. for all three methods, after the clock-stop state is released, the program starts from address 0000h. # raising the ce pin from low level to high level (ce reset) $ raising the p1b 2 /rls stp pin from low level to high level % dropping v dd to 2.2 v or less, then raising it to 4.5 v (power-on reset) to use the p1b 2 /rls stp pin to release the clock-stop state, the rlsen flag of the control register must be set. 19.3.3 clock-stop release by ce reset fig. 19-3 shows the clock-stop release by ce reset.
288 m pd17068 fig. 19-3 clock-stop release by ce reset 19.3.4 clock-stop release by power-on reset fig. 19-4 shows the clock-stop release by power-on reset. if the clock-stop state is released by power-on reset, the power failure detection circuit operates. fig. 19-4 clock-stop release by power-on reset 5 v 0 v v dd h l h l ce pin x out pin stop s instruction approx. 50 ms program starts at address 0 (power-on reset) 5 v 0 v v dd h l h l ce pin x out pin if a clock-stop instruction is not used, operation is as follows: approx. 50 ms program starts at address 0 (power-on reset) oscillation stopped 3.5 v 2.2 v 5 v 0 v v dd h l h l ce pin x out pin stop s instruction approx. 50 ms program starts at address 0 (ce reset) 5 v 0 v v dd h l h l ce pin x out pin if a clock-stop instruction is not used, operation is as follows: 0-t set program starts at address 0 (ce reset) ce reset is applied in synchronization with the setting of the timer carry flip-flop after the ce pin has been raised to high level.
289 m pd17068 19.3.5 clock-stop release by r1b 2 /rls stp pin when the stop-clock state is released by the p1b 2 /rls stp pin, the rlsen flag of the clock-stop release enable register must be set. the rising edge of the p1b 2 /rls stp pin input can be detected by monitoring the p1b2edet flag of the p1b 2 pin edge detection register. fig. 19-5 shows the organization and functions of the clock-stop release enable register. fig. 19-6 shows the organization and functions of the p1b 2 pin edge detection register. fig. 19-5 configuration of clock-stop release enable register register flag symbol b 3 b 2 b 1 b 0 r l s e n 20h r/w address read/write upon reset power-on clock stop ce 00 0 1 sets clock-stop release by p1b 2 /rls stp pin. do not release. release at rising edge of signal. 00 0 fixed to 0. clock-stop release enable register 0 0 hold hold
290 m pd17068 fig. 19-6 configuration of p1b 2 pin edge detection register register flag symbol b 3 b 2 b 1 b 0 p 1 b 2 e d e t 34h r & reset address read/write upon reset power-on clock stop ce 00 0 1 detects the rising edge input to the p1b 2 /rls stp pin. rising edge not input. rising edge input. 00 0 fixed to 0. p1b 2 pin edge detection register 0 0
291 m pd17068 19.3.6 cautions when using clock-stop instruction the clock-stop instruction (stop s instruction) is valid only when the ce pin is low level. the program must take into account processing when the ce pin is raised unexpectedly to high level. the description is based on the following example. example xtal dat 0000b ; clock-stop condition symbol definition cejdg : ; # skf1 ce ; built-in macro ; detects the ce pin input level. br main ; if ce = high level, branches to main processing. process a ; ce = low level processing ; $ stop xtal ; clock-stop ; % br $ C 1 main : main processing br cejdg in the example above, the state of the ce pin is detected at # . if the ce pin is low level, after process a is executed, the clock-stop instruction stop xtal of $ is executed. however, if the ce pin becomes high level while the stop xtal instruction of $ is being executed as shown in the figure below, the stop xtal instruction operates as a no operation instruction (nop). if the branch instruction br $-1 of % does not exit, the program returns to main processing and erroneous operational occurs. therefore, a branch instruction like % must be inserted in the program, or the program must be written so that erroneous operational does not occur even if it returns to main processing. when a branch instruction like % is used, ce reset is applied in synchronization with the next setting of the carry flip-flop of basic timer 0, even if the ce pin remains at high level. 5 v 0 v h l v dd ce pin ## # $ stop xtal the stop xtal becomes a nop instruction because the ce pin is high level. the program starts from address 0 in synchronization with setting of the carry flip- flop of basic timer 0. (ce reset) main proces- sing process a ce pin detection
292 m pd17068 19.4 device operation at halt and clock-stop table 19-1 shows the operation of the cpu and peripheral hardware in the halt state and clock-stop state. in the halt state, all the peripheral hardware units continue to operate normally except that they stop executing instructions. in the clock-stop state, all the peripheral hardware units stop operating. in the halt state, the control register that controls the operating state of the peripheral hardware operates normally (not initialized). however, when a clock-stop instruction is executed, it is initialized to the specified value. in short, in the halt state, the operation set in the control register continues and in the clock-stop state, the operating state is determined in accordance with the initialized control register value. for the control register value in the clock-stop state, see section 8. a sample program is shown below. example program that specifies the p0a 0 /sda and p0a 1 /scl pins as input ports and uses the p0a 2 /sck 0 and p0a 3 /so 0 pins as a serial interface. hltint dat 1000b xtal dat 0000b initflg p0abio3, p0abio2, p0abio1, p0abio0 ; # set2 p0a1, p0a0 initflg sio0ch, not sb, sio0ms, sio0tx set2 sio0ck1, siock0 ; $ initflg not sio0imd1, sio0imd0 clr1 irqsio0 set1 ipsio0 ei ; % set1 sio0nwt ; & halt hltint ; ( stop xtal in the example, # outputs high level from the p0a 1 and p0a 0 pins, $ sets the serial interface 0 conditions, and % starts serial communication. when the halt instruction is executed at & , serial communication continues, and the halt state is released when a serial interface 0 interrupt is received. if the stop instruction of ( is executed instead of the halt instruction of & , all the flags of the control register set at # , $ and % are initialized. serial communication is terminated and all the port 0a pins are made general-purpose input ports.
293 m pd17068 table 19-1 device operation in halt state and clock-stop state state peripheral hardware ce pin: high level ce pin: low level at halt at clock-stop at halt at clock-stop program counter stopped at halt stopped at halt initialized to 0000h instruction address. instruction address. and stopped. system register held held initialized note peripheral register held held held control register held held initialized note timers other than watchdog timer normal operation normal operation operation stopped watchdog timer normal operation normal operation normal operation normal operation pll frequency synthesizer normal operation disabled operation stopped a/d converter normal operation normal operation operation stopped d/a converter normal operation normal operation operation stopped serial interface normal operation normal operation operation stopped idc normal operation operation stopped operation stopped horizontal synchronizing signal counter normal operation normal operation operation stopped general-purpose i/o port normal operation normal operation input port general-purpose input port normal operation normal operation input port general-purpose output port normal operation normal operation held stop instruction invalid (nop) stop instruction invalid (nop) note for the value that is initialized, see sections 5 and 8. 19.5 pin processing cautions in halt state and clock-stop state the halt state is used to reduce the supply current when only the clock is operating. the clock-stop function is used to reduce the supply current for holding only the data memory. consequently, the supply current must be reduced as much as possible in the halt and clock-stop states. the supply current depends on the state of each pin and the cautions shown in table 19-2 must be observed.
294 m pd17068 table 19-2 state of each pin and cautions in halt and clock-stop states (1/2) the state before halt is held. (1) when specified as output pins if externally pulled down while high level is being output or if externally pulled up while low level is being output, the supply current increases. (2) when specified as input pins when floating, noise, etc. increase the drain current. (3) port 0d since a pull-down resistor is built in, when externally pulled up, the drain current increases. all pins are specified as general- purpose input pins. port 0d is internally pulled down. output ports. the output contents are held. if externally pulled down while high level is being output or if externally pulled up while low level is being output, the supply current increases. general-purpose output port general-purpose input port pin function pin symbol state of each pin and processing cautions halt state clock-stop state port 0a p0a 3 /so 0 p0a 2 /sck 0 p0a 1 /scl p0a 0 /sda port 0b p0b 3 /hscnt p0b 2 /i p0b 1 p0b 0 /si 0 port 1b p1b 3 /tmin p1b 2 /rls stp p1b 1 /ckout p1b 0 port 1c p1c 3 p1c 2 /adc 7 p1c 1 /adc 6 p1c 0 /adc 5 port 2d p2d 2 /si 1 p2d 1 /so 1 p2d 0 /sck 1 port 0d p0d 3 /adc 4 p0d 2 /adc 3 p0d 1 /adc 2 /xt in p0d 0 /adc 1 /xt out port 0c p0c 3 p0c 2 p0c 1 p0c 0 port 1a p1a 3 p1a 2 p1a 1 p1a 0 port 1d p1d 3 p1d 2 p1d 1 p1d 0 port 2a p2a 0 /pwm 8 port 2b p2b 3 /pwm 7 p2b 2 /pwm 6 p2b 1 /pwm 5 p2b 0 /pwm 4 port 2c p2c 3 /pwm 3 p2c 2 /pwm 2 p2c 1 /pwm 1 p2c 0 /pwm 0 general-purpose i/o port
295 m pd17068 table 19-2 state of each pin and cautions in halt and clock-stop states (2/2) pin function pin symbol state of each pin and processing cautions halt state clock-stop state external interrupt int nc when floating, noise, etc. increase the supply current. int 0 pll frequency vco at pll operation, the supply current pll disabled state. synthesizer eo increases. the state when pll is vco : pulled down internally psc disabled is shown below. eo : floating vco : pulled down internally psc : low level output eo : floating psc : low level output when the ce pin becomes low level, the pll is automatically disabled. image display red the state before halt is held. red controller (idc) green green blue blue blank blank p0b 2 /i p0b 2 /i specified general-purpose input port. crystal oscillation x in the supply current changes with the x in pin is pulled down inter- circuit x out the oscillation waveform of the nally and the x out pin outputs crystal oscillation circuit. high level. the larger the oscillation amplitude, the lower the supply current. since the oscillation amplitude is governed by the crystal and load capacitor used, evaluation is necessary. low level output
296 m pd17068 19.6 device operation control by ce pin the ce pin controls the following functions by means of the input level and rising edge of a signal received from the outside: (1) image display controller (idc) (2) pll frequency synthesizer (3) clock-stop instruction disable/enable (4) device reset 19.6.1 image display controller (idc) operation control the idc can operate only when the ce pin is high level. when the ce pin is low level, the oscillation circuit stops automatically. 19.6.2 pll frequency synthesizer operation control the pll frequency synthesizer can operate only when the ce pin is high level. when the ce pin is low level, the vco pin is pulled down inside the device and the eo pin is floated. for details, see section 18.5. the pll frequency synthesizer can be disabled by program even when the ce pin is high level. 19.6.3 clock-stop instruction disable/enable control the clock-stop instruction (stop s instruction) is valid only when the ce pin is low level. if the ce pin is high level, the clock-stop instruction is executed as a no operation instruction (nop). 19.6.4 device reset reset (ce reset) can be applied to the device by raising the ce pin from low level to high level. besides ce reset, there is also power-on reset, which is activated when v dd is turned on. for details, see section 20.
297 m pd17068 19.6.5 signal input to ce pin to prevent erroneous operation by noise, the ce pin does not accept signals with a low or high level width of less than 110 to 165 m s. the level of the signal input to the ce pin can be detected with the ce flag of the ce pin level judge register (rf address 07h). fig. 19-7 shows the relationship between input signal and ce flag. fig. 19-7 relationship of signal input to ce pin and ce flag 19.6.6 organization and functions of ce pin level judge register the ce pin level judge register monitors the ce pin input signal level. its organization and functions are shown below. fig. 19-8 configuration of ce pin level judge register the ce flag also does not change when the ce pin receives signals having a low or high level width of less than 110 to 165 m s. h l ce pin ce flag 1 0 110 to 165 s 110 to 165 s 110 to 165 s 110 to 165 s ce reset pll operation enabled idc operation enabled stop s instruction invalid (nop) pll disabled idc operation stopped stop s instruction valid pll disabled idc operation stopped stop s instruction invalid (nop) ce reset is applied in synchronization with the next setting of the carry flip-flop of basic timer 0. register flag symbol b 3 b 2 b 1 b 0 c e 07h r address read/write upon reset power-on clock stop ce 00 0 1 monitors the level input at the ce pin. low level input high level input 0 0 fixed to 0. ce pin level judge register 0 0
298 m pd17068 19.6.7 organization and functions of ce pin edge detection register the ce pin edge detection register detects the rising edge of the signal applied to the ce pin. its organization and functions are shown below. fig. 19-9 configuration of ce pin edge detection register remark the ceedet flag does not change when the ce pin receives signals having a low or high level width of less than 110 to 165 m s. register flag symbol b 3 b 2 b 1 b 0 c e e d e t 02h r & reset address read/write upon reset power-on clock stop ce 00 0 1 detects the rising edge input at the ce pin. rising edge not input rising edge input 00 0 fixed to 0. ce pin detection register 0 0
299 m pd17068 20. reset the reset function is used to initialize device operation. 20.1 reset block configuration fig. 20-1 shows the configuration of the reset block. device reset is divided into reset by turning on v dd (power-on reset or v dd reset), and reset by ce pin (ce reset). the power-on reset block consists of a voltage detection circuit that detects the voltage applied to the v dd pin, a power failure detection circuit, and a reset control circuit. the ce reset block consists of a circuit that detects the rising edge of the signal input to the ce pin, and a reset control circuit. fig. 20-1 reset block x out x in v dd ce power-on clear signal (poc) reset signal ires res reset stop instruction r s q selector basic timer 0 carry timer flip-flop block power failure detection block scaler btm0cy flag read stop s instruction voltage detection circuit control register system register stack program counter forced halt by basic timer 0 carry rising edge detection circuit basic timer 0 carry disable flip-flop reset control circuit
300 m pd17068 20.2 reset function power-on reset is applied when v dd rises from a certain voltage. ce reset is applied when the ce pin rises from low level to high level. power-on reset initializes the program counter, stack, system register and control registers, and executes the program from address 0000h. ce reset initializes the program counter, stack, system register and some control registers, and executes the program from address 0000h. the main differences between power-on reset and ce reset are the operation of the control registers that are initialized and the power failure detection circuit described in section 20.6 . power-on reset and ce reset are controlled by reset signals ires, res, and reset output from the reset control circuit in fig. 20-1. table 20-1 shows the ires, res, and reset signal and power-on reset and ce reset relationship. the reset control circuit also operates when the clock-stop instruction (stop s) described in section 19 is executed. sections 20.3 and 20.4 describe ce reset and power-on reset, respectively. section 20.5 describes the relationship between ce reset and power-on reset. table 20-1 relationship between internal reset signal and each reset output signal internal reset signal at ce reset at power- at clock-stop contents controlled by each reset signal on reset ires l l l l forces the device into the halt state. the halt state is released by the setting of the carry flip-flop of basic timer 0. res l l l l initializes some control registers. reset l l l l l l initializes the program counter, stack, system register, and some control registers.
301 m pd17068 20.3 ce reset ce reset is executed by raising the ce pin from low level to high level. when the ce pin rises to high level, the reset signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the carry flip-flop of basic timer 0. when ce reset is applied, the reset signal initializes the program counter, stack, system register, and some control registers to their initial value and executes the program from address 0000h. for the initial values, see the relevant item. ce reset operation is different when clock-stop is used and when it is not used. these operations are described in sections 20.3.1 and 20.3.2 , respectively. section 20.3.3 describes the cautions at ce reset. 20.3.1 ce reset when clock-stop (stop s instruction) not used fig. 20-2 shows the reset operation. when clock-stop (stop s instruction) is not used, the basic timer 0 clock selection register of the control registers is not initialized. therefore, after the ce pin becomes high level, the reset signal is output, and reset is applied at the rising edge of the selected pulse (1 ms, 5 ms, or 100 ms) used for setting the carry flip-flop of basic timer 0. fig. 20-2 ce reset operation when clock-stop not used 5 v 0 v h l h l h l h l h l h l normal operation normal operation x out v dd ce pulse used for setting the carry flip-flop of basic timer 0. ires res reset reset signal ce reset is applied at the rising edge of the pulse used for setting the carry flip-flop of basic timer 0. this period, t, varies with the timing when the ce pin signal rises. it falls in the range from 0 to t set (0 < t < t set ), which is the selected set time of the carry flip-flop of basic timer 0. the program continues to run during this period.
302 m pd17068 20.3.2 ce reset when clock-stop (stop s instruction) used fig. 20-3 shows the reset operation. when clock-stop is used, the ires, res and reset signals are output at the time the stop s instruction is executed. at this time, the res signal initializes the basic timer 0 clock selection register of the control registers to 0000b and sets the basic timer 0 carry flip-flop setting signal to 100 ms. since the ires signal is output continuously while the ce pin is low level, release by basic timer 0 carry is forcibly halted. since the clock itself stops, the device stops operating. when the ce pin rises to high level, the clock-stop state is released and oscillation begins. the ires signal halts release by basic timer 0 carry. when the pulse used for setting the carry flip-flop of basic timer 0 rises after the ce pin rises, the halt state is released and the program starts from address 0. since the basic timer 0 carry flip-flop setting pulse is initialized to 100 ms, ce reset is applied 50 ms after the ce pin rises to high level. fig. 20-3 ce reset operation when clock-stop used 5 v 0 v h l h l h l h l h l h l normal operation clock-stop state x out v dd ce basic timer 0 carry flip-flop setting pulse ires res reset reset signal ce reset program starts from address 0. clock stop release oscillation start stop s instruction halt state 50 ms
303 m pd17068 20.3.3 cautions at ce reset when ce reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) time required for clock and other timer processing when writing a clock program by using basic timer 0 carry and basic timer 2 interrupts, the program must end processing within a certain time. for details, see sections 12.2.6 and 12.4.5. (2) processing of data, flags, etc. used in the program care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one instruction so that the contents do not change even when ce reset is applied.
304 m pd17068 20.4 power-on reset power-on reset is executed by raising v dd from a certain voltage (called the power-on clear voltage) or less. when v dd is less than the power-on clear voltage, the power-on clear signal (poc) is output from the voltage detection circuit shown in fig. 20-1. when the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating. while the power-on clear signal is being output, the ires, res and reset signals are output. when v dd exceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation starts. at the same time, the ires, res and reset signals are also dropped. since the ires signal halts release by basic timer 0 carry, power-on reset is applied at the rising edge of the next basic timer 0 carry flip-flop setting signal. since the reset signal has initialized the basic timer 0 carry flip-flop setting signal to 100 ms, 50 ms after v dd exceeds the power-on clear voltage, reset is applied and the program starts from address 0. this operation is shown in fig. 20-4. at power-on reset, the program counter, stack, system register and control registers are initialized when the power-on clear signal is output. for the initial values, see the relevant items. during normal operation, the power-on clear voltage is 3.5 v (rated value). in the clock-stop state, the power-on clear voltage becomes 2.2 v (rated value). sections 20.4.1 and 20.4.2 describe operation at this time. section 20.4.3 describes operation when v dd rises from 0 v, fig. 20.4 power-on reset operation 5 v 0 v h l h l h l h l h l h l normal operation device operation stopped x out v dd ce basic timer 0 carry flip-flop setting pulse ires res reset reset signal power-on reset program starts from address 0 h l power-on clear signal power-on clear release oscillation start halt state 50 ms power-on clear voltage
305 m pd17068 20.4.1 power-on reset at normal operation fig. 20-5 (a) shows power-on reset at normal operation. as shown in fig. 20-5 (a), when the v dd drops below 3.5 v, the power-on clear signal is output and operation of the device stops regardless of the input level of the ce pin. when v dd then rises to 3.5 v or greater, after a 50 ms halt, the program starts from address 0000h. normal operation refers to the state in which the clock-stop instruction is not used. this also includes the halt state set by the halt instruction. 20.4.2 power-on reset in clock-stop state fig. 20-5 (b) shows power-on reset in the clock-stop state. as shown in fig. 20-5 (b), when v dd drops below 2.2 v, the power-on clear signal is output and device operation stops. however, since the device is in the clock-stop state, its operation apparently does not change. when v dd rises to 3.5 v or greater, after a 50 ms halt, the program starts from address 0000h. 20.4.3 power-on reset when v dd rises from 0 v fig. 20-5 (c) shows power-on reset when v dd rises from 0 v. as shown in fig. 20-5 (c), the power-on clear signal is being output while v dd is rising from 0 v to 3.5 v. when v dd rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 50 ms halt, the program starts from address 0000h.
306 m pd17068 fig. 20-5 power-on reset and v dd (a) during normal operation (including halt state) (b) at clock-stop (c) when v dd rises from 0 v 5 v 0 v h l h l h l clock-stop device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms 2.2 v power-on clear voltage 3.5 v stop s instruction normal operation 5 v 0 v h l h l h l device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms 3.5 v power-on clear voltage 5 v 0 v h l h l h l normal operation device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms power-on clear voltage 3.5 v
307 m pd17068 20.5 relationship between ce reset and power-on reset when v dd is first turned on, power-on reset and ce reset may be applied simultaneously. sections 20.5.1 through 20.5.3 describe this reset operation. section 20.5.4 describes the cautions when v dd rises. 20.5.1 when v dd pin and ce pin rise simultaneously fig. 20-6 (a) shows the reset operation. power-on reset starts the program from address 0000h. 20.5.2 when ce pin raised in forced halt state caused by power-on reset. fig. 20-6 (b) shows the reset operation. power-on reset starts the program from address 0000h, as in section 20.5.1. 20.5.3 when ce pin raised after power-on reset fig. 20-6 (c) shows the reset operation. power-on reset starts the program from address 0000h. ce reset restarts the program from address 0000h at the rising edge of the next basic timer 0 carry flip-flop setting signal.
308 m pd17068 fig. 20-6 relationship between power-on reset and ce reset (a) when v dd and ce pin raised simultaneously (b) when ce pin raised in halt state (c) when ce pin raised after power-on reset 5 v 0 v h l h l opera- tion stopped v dd ce power-on reset program start power-on clear voltage 3.5 v halt state 50ms normal operation basic timer 0 carry flip-flop setting pulse 5 v 0 v h l h l v dd ce power-on reset program start power-on clear voltage 3.5 v halt state 50 ms normal operation basic timer 0 carry flip-flop setting pulse opera- tion stopped 5 v 0 v h l h l v dd ce basic timer 0 carry flip-flop setting pulse power-on reset program start power-on clear voltage 3.5 v halt state 50 ms normal operation ce reset program start opera- tion stopped
309 m pd17068 20.5.4 cautions when v dd raised when v dd is raised, careful attention must be given to points (1) and (2) below. (1) when v dd raised from power-on clear voltage when v dd is raised, it must raised to 3.5 v or greater, once. this is shown in fig. 20-7. as shown in fig. 20-7, when a voltage under 3.5 v is applied when v dd is turned on in a program that uses clock-stop to back up v dd at 2.2 v, for example, the power-on clear signal continues to be output and the program does not run. since the device output port outputs an undefined value, the supply current increases, according to the situation, reducing the back-up time with a battery considerably. fig. 20-7 caution when v dd raised 5 v 0 v h l h l h l h l operation stopped x out v dd ce power-on clear signal basic timer 0 carry flip-flop setting pulse 3.5 v 2.2 v opera- tion stopped halt state 50 ms normal operation back-up since the values of the output ports, etc. are undefined during this period, the supply current may increase. during this period, initialization is per- formed, then the clock is stopped. power-on reset program start stop s instruction power-on clear voltage
310 m pd17068 (2) at return from clock-stop state when returning from the back-up state when clock-stop is used to back-up v dd at 2.2 v, v dd must be raised to 3.5 v or greater within 50 ms after the ce pin becomes high level. as shown in fig. 20-8, return from the clock-stop state is performed by ce reset. since the power-on clear voltage is switched to 3.5 v 50 ms after the ce pin is raised, if v dd is not 3.5 v or greater at this time, power- on reset is applied. the same caution is necessary when v dd is dropped. fig. 20-8 return from clock-stop state 5 v 0 v h l h l h l h l x out v dd ce power-on clear signal basic timer 0 carry flip-flop setting pulse 3.5 v 2.2 v ce=low processing normal operation back-up back-up caused by clock stop power-on clear voltage halt state 50 ms ce reset program start stop s instruction at this point, the power-on clear voltage is switched to 2.2 v. therefore, v dd must not be dropped below 3.5 v before this point. at this point, the power-on clear voltage is switched to 3.5 v. therefore, v dd must be raised to 3.5 v or greater before this point.
311 m pd17068 20.6 power failure detection power failure detection is used to judge whether the device is reset by turning on v dd or by the ce pin, as shown in fig. 20-9. since the contents of the data memory, output ports, etc. become undefined when v dd is turned on, they are initialized by power failure detection. there are two power failure detection methods. one method detects a power failure by using a power failure detection circuit to detect the btm0cy flag and the other method detects the contents of the data memory (ram judgment). sections 20.6.1 and 20.6.2 describe the power failure detection circuit, and power failure detection by btm0cy flag, respectively. sections 20.6.3 and 20.6.4 describe power failure detection with the ram judgment method. fig. 20-9 power failure detection flowchart 20.6.1 power failure detection circuit as shown in fig. 20-1, the power failure detection circuit consists of a voltage detection circuit and timer carry disable flip-flop that is reset by the output (power-on clear signal) of the voltage detection circuit, and basic timer 0 carry. the basic timer 0 carry disable flip-flop is set (1) by the power-on clear signal and is reset (0) when a btm0cy flag read instruction is executed. when the basic timer 0 carry disable flip-flop is set (1), the btm0cy flag is not set (1). that is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which the btm0cy flag is reset and the setting disabled state is set until a btm0cy read instruction is executed thereafter. once a btm0cy read instruction is executed, the btm0cy flag is set at each rising edge of the basic timer 0 carry flip-flop setting pulse thereafter. when reset is applied to the device, the contents of the btm0cy flag are monitored. if the btm0cy flag has been reset (0), power-on reset (power failure) is judged and if the btm0cy flag has been set (1), ce reset (no power failure) is judged. since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, v dd becomes 3.5 v at crystal oscillation and 2.2 v at clock-stop. fig. 20-10 shows the btm0cy flag state transition. fig. 20-11 shows timing chart and btm0cy flag operation specified in fig. 20-10. program start power failure detect- ion power failure no power failure data memory, output port, etc. initialization
312 m pd17068 fig. 20-10 btm0cy flag state transition # $ v dd = l ? 3.5 v ce = 1 ce = h ( &)* + , -. 0 /12 3 4 ce = h ? l stop0 btm0cy = 0 ce = l ? h ce = l ? h ce = h ? l ce = l ? h ce = l ? h stop0 btm0cy = 1 ce = low ce = optional ce = high v dd = low operation stopped crystal oscillation start forced halt (approx. 50 ms) power-on reset normal operation ce reset rising edge of basic timer 0 carry flip-flop setting pulse clock-stop btm0cy flag setting disabled state normal operation normal operation ce set wait crystal oscillation start forced halt (50 ms) skt1 btm0cy or skf1 btm0cy skt1 btm0cy or skf1 btm0cy normal operation ce reset rising edge of basic timer 0 carry flip-flop setting pulse clock-stop normal operation normal operation ce set wait crystal oscillation start forced halt (50 ms) btm0cy flag setting enable state
313 m pd17068 fig. 20-11 btm0cy flag operation (a) when btm0cy flag not detected even once (neither skt1 btm0cy nor skf1 btm0cy executed) (b) when power failure detected with btm0cy flag 5v 0v h l h l h l v dd ce basic timer 0 carry flip-flop setting pulse btm0cy fig. 20-10 operation timer time switching stop 0000 b #$)(+ ) (&, ) # * * % 5v 0v h l h l h l v dd ce basic timer 0 carry flip-flop setting pulse btm0cy skt1 instruction timer time switching stop 0000 b # % fig. 20-10 operation $)1 0 3 1 0 / 4 1 # btm0cy=0 power failure btm0cy=1 no power failure btm0cy=1 no power failure 2 2 .
314 m pd17068 20.6.2 cautions at power failure detection with btm0cy flag when clock counting, etc. is performed with the btm0cy flag, careful attention must be given to the following points. (1) clock updating when writing a clock program by using basic timer 0, the clock must be updated after a power failure. this is because the btm0cy flag is reset (0) and one clock count is lost by btm0cy flag reading when a power failure is detected. (2) clock update processing time when the clock is updated, its processing must end before the next rising edge of the basic timer 0 flip- flop setting pulse. this is because if the ce pin rises to high level during clock update processing, the clock update processing will not be executed up to the end and a ce reset will be applied. for (1) and (2) above, see section 12.2.6 (3). when processing is performed at a power failure, careful attention must be given to the following point. (3) power failure detection timing when clock counting, etc. is performed with the btm0cy flag, the flag must be read for power-failure detection before the next rising edge of the basic timer 0 carry flip-flop setting pulse, after a program starts from address 0000h. this is because when the basic timer 0 carry flip-flop setting time is set to 5 ms, for instance, and power failure detection is performed 6 ms after the program starts, one btm0cy flag is lost. see section 12.2.6 (3). as shown in the example on the next page, power failure detection and initialization must be performed within the basic timer 0 carry flip-flop set time. this is because when the ce pin is raised and ce reset is applied during power failure processing and initialization, these processings are interrupted and a problem may occur. when the basic timer 0 carry flip-flop set time is changed in initialization, an instruction that makes the change must be executed at the end of initialization. this is also because when the basic timer 0 carry flip-flop set time is switched before initialization as shown in the example on the next page, initialization by ce reset may not be executed up to the end.
315 m pd17068 example sample program start: ; program address 0000h ; # reset processing ; $ skt1 btm0cy ; power failure detection br initial backup: ; % clock updating br main initial: ; & initialization ; ( initflg not btm0ck1, btm0ck0 ; built-in macro ; sets basic timer 0 carry flip-flop set time to 5 ms. main: main process skt1 btm0cy br main clock updating br main operation example 5v 0v h l h l v dd ce basic timer 0 carry flip-flop setting pulse # 50 ms 50 ms $ power failure detection &#% $ power failure detection ce reset ce reset when the processing time of # + % is too long, a ce reset is applied. when the processing time of # + & is 100 ms or longer, a ce reset is applied midway through processing 4. ( ce reset may be applied immediately, depending on the basic timer 0 carry flip-flop set time switching timing. when ( is executed before & , power failure processing & may not be executed up to the end.
316 m pd17068 20.6.3 power failure detection by ram judgment the ram judgment method detects a power failure by judging if the contents of the data memory at a specified address are the specified value when the device was reset. a sample program that detects a power failure by ram judgment is shown on the next page. the contents of data memory when v dd is turned on are undefined. the ram judgment method performs power failure detection by comparing the undefined value with the specified value. therefore, power failure detection may be judged erroneously, as described in section 20.6.4. however, the advantage of using the ram judgment method is that, as shown in table 20-2, back-up down to a lower voltage than that detected by power detection circuit is possible. table 20-2 comparison of power failure judgment circuit and power failure detection by ram judgment power failure detection circuit ram judgment actual value rating actual value rating 2 C 2.2 v 2.2 v 0 C 1 v 2.2 v remarks no erroneous operation erroneous operation possible data hold voltage (at clock-stop)
317 m pd17068 sample program which detects power failure by ram judgment m012 mem 0.12h m034 mem 0.34h m056 mem 0.56h m107 mem 1.07h m128 mem 1.28h m16f mem 1.6fh data0 dat 1010b data1 dat 0101b data2 dat 0110b data3 dat 1001b data4 dat 1100b data5 dat 0011b start: set2 cmp, z sub m012, #data0 ; if m012 = data0 and sub m034, #data1 ; m034 = data1 and sub m056, #data2 ; m056 = data2 and bank1 sub m107, #data3 ; m107 = data3 and sub m128, #data4 ; m128 = data4 and sub m16f, #data5 ; m16f = data5 bank0 skf1 z br backup ; branches to backup ; initial: initialization mov m012, #data0 mov m034, #data1 mov m056, #data2 bank1 mov m107, #data3 mov m128, #data4 mov m16f, #data5 br main backup: back-up processing main: main processing
318 m pd17068 20.6.4 cautions at power failure detection by ram judgment since the data memory value when v dd is turned on is undefined, careful attention must be given to points (1) and (2) below. (1) comparison data when n bits of data memory is to be compared by ram judgment, the probability that the data memory value when v dd is turned on may unexpectedly match the specified value is (1/2) n . that is, there is a (1/2) n probability that power failure detection by ram judgment will be judged back- up. to reduce this probability, the largest number of bits possible are compared. since, from experience, the contents of data memory when v dd is turned on easily becomes the same value, such as 0000b and 1111b, comparison data that mixes 0 and 1, such as 1010b and 0110b, reduces the possibility of erroneous judgment. (2) program cautions when v dd is raised from a voltage that begins to destroy the data memory as shown in fig. 20-12, even if the value of data memory to be compared is normal, other values may be destroyed. since power failure detection by ram judgment judges it as back-up, the program must be written so that it does not crash even if the data memory is destroyed. fig. 20-12 v dd and destruction of data memory 5v 0v v dd data memory destruction start voltage data memory ram judgment data memory (normal) the value of the data memory not used in ram judgment may be destroyed.
319 m pd17068 21. instruction set 21.1 list of instruction set b 15 b 14 -b 11 0 1 bin hex 0 0 0 0 0 add r, m add m, #n4 0 0 0 1 1 sub r, m sub m, #n4 0 0 1 0 2 addc r, m addc m, #n4 0 0 1 1 3 subc r, m subc m, #n4 0 1 0 0 4 and r, m and m, #n4 0 1 0 1 5 xor r, m xor m, #n4 0 1 1 0 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar syscal entry ret retsk ei di 0111 7 reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1 0 0 0 8 ld r, m st m, r 1 0 0 1 9 ske m, #n4 skge m, #n4 1 0 1 0 a mov @r, m mov m, @r 1 0 1 1 b skne m, #n4 sklt m, #n4 1 1 0 0 c br addr (page 0) call addr (page 0) 1 1 0 1 d br addr (page 1) mov m, #n4 1 1 1 0 e br addr (page 2) skt m, #n 1111 f br addr (page 3) skf m, #n
320 m pd17068 21.2 instructions legend ar : address register asr : address stack register pointed to by the stack pointer addr : program memory address (11 low-order bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer entry : program memory address (bits 10 to 8, bits 3 to 0) entry h : program memory address (bits 10 to 8) entry l : program memory address (bits 3 to 0) h : halt release condition intef : interrupt enable flag intr : register automatically saved in the stack when an interrupt occurs intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address specified by m r and m c m r : data memory row address (high-order) m c : data memory column address (low-order) n : bit position (four bits) n4 : immediate data (four bits) page : page (bits 12 and 11 of the program counter) pc : program counter p : peripheral address p h : peripheral address (three high-order bits) p l : peripheral address (four low-order bits) r : general register column address rf : register file address rf r : register file address (three high-order bits) rf c : register file address (four low-order bits) sgr : segment register (bit 13 of the program counter) sp : stack pointer s : stop release condition wr : window register ( ) : contents of
321 m pd17068 instruction set add subtract logical operation test compare rotation transfer mne- monic add addc inc sub subc or and xor skt skf ske skne skge sklt rorc ld st mov movt operand r, m m, #n4 r, m m, #n4 ar ix r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r r, m m, r @r, m m, @r m, #n4 dbf, @ar instruction code op code 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 01000 11000 01010 11010 11101 00111 operand m r m r m r m r 000 000 m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r 000 m r m r m r m r m r 000 m c m c m c m c 1001 1000 m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c 0111 m c m c m c m c m c 0001 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r r r r r n4 0000 operation (r) ? (r) + (m) (m) ? (m) + n4 (r) ? (r) + (m) + cy (m) ? (m) + n4 + cy ar ? ar + 1 ix ? ix + 1 (r) ? (r) C (m) (m) ? (m) C n4 (r) ? (r) C (m) C cy (m) ? (m) C n4 C cy (r) ? (r) (m) (m) ? (m) n4 (r) ? (r) (m) (m) ? (m) n4 (r) ? (r) (m) (m) ? (m) n4 cmp ? 0, if (m) n = n, then skip cmp ? 0, if (m) n = 0, then skip (m) C n4, skip if zero (m) C n4, skip if not zero (m) C n4, skip if not borrow (m) C n4, skip if borrow ? cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 (r) ? (m) (m) ? (r) if mpe = 1: (mp, (r)) ? (m) if mpe = 0: (bank, m r , (r)) ? (m) if mpe = 1: (m) ? (mp, (r)) if mpe = 0: (m) ? (bank, m r , (r)) (m) ? n4 sp ? sp C 1, asr ? pc, pc ? ar, dbf ? (pc), pc ? asr, sp ? sp + 1
322 m pd17068 instruction code mne- monic push pop peek poke get put br call syscal ret retsk reti ei di stop halt nop operand ar ar wr, rf rf, wr dbf, p p, dbf addr @ar addr @ar entry s h instruction set transfer branch sub- routine interrupt others op code 00111 00111 00111 00111 00111 00111 01100 01101 01110 01111 00111 11100 00111 00111 00111 00111 00111 00111 00111 00111 00111 00111 000 000 rf r rf r p h p h 000 000 entry h 000 000 100 000 001 010 011 100 0000 0000 rf c rf c p l p l 0000 0000 entry l 0000 0000 0000 0000 0000 s h 0000 1101 1100 0011 0010 1011 1010 0100 0101 0000 0101 1110 1110 1111 1111 1111 1111 1111 operation operand addr addr sp ? sp C 1, asr ? ar ar ? asr, sp ? sp + 1 wr ? (rf) (rf) ? wr dbf ? (p) (p) ? dbf pc 10-0 ? addr, page ? 0 pc 10-0 ? addr, page ? 1 pc 10-0 ? addr, page ? 2 pc 10-0 ? addr, page ? 3 pc ? ar sp ? sp C 1, asr ? pc, pc 12,11 ? 0, pc 10-0 ? addr sp ? sp C 1, asr ? pc, pc ? ar sp ? sp C 1, asr ? pc, sgr ? 1, pc 12,11 ? 0, pc 10-8 ? entry h , pc 7-4 ? 0, pc 3-0 ? entry l pc ? asr, sp ? sp + 1 pc ? asr, sp ? sp + 1 and skip pc ? asr, intr ? intsk, sp ? sp + 1 intef ? 1 intef ? 0 stop halt no operation
323 m pd17068 21.3 assembler (as17k) built-in macro instructions legend flag n : flg-type symbol < > : an operand enclosed in < > is optional. mnemonic operand operation n built-in sktn flag 1, flag n if (flag 1) to (flag n) = all 1, then skip 1 n 4 skfn flag 1, flag n if (flag 1) to (flag n) = all 0, then skip 1 n 4 setn flag 1, flag n (flag 1) to (flag n) ? 11 n 4 clrn flag 1, flag n (flag 1) to (flag n) ? 01 n 4 notn flag 1, flag n if (flag n) = 0, then (flag n ) ? 11 n 4 if (flag n) = 1, then (flag n) ? 0 initflg flag 1, if description = not flag n, then (flag n ) ? 01 n 4 <flag n> if description = flag n, then (flag n) ? 1 bankn (bank) ? n0 n 2 macro
324 m pd17068 22. reserved symbols 22.1 data buffer (dbf) dbf3 dbf2 dbf1 dbf0 mem mem mem mem 0.0ch 0.0dh 0.0eh 0.0fh r/w r/w r/w r/w dbf bits 15 to 12 dbf bits 11 to 8 dbf bits 7 to 4 dbf bits 3 to 0 read/ write description symbol attribute value 22.2 system register (sysreg) mem mem mem mem mem mem mem mem flg mem mem mem mem mem mem flg flg flg flg flg 0.74h 0.75h 0.76h 0.77h 0.78h 0.79h 0.7ah 0.7ah 0.7ah.3 0.7bh 0.7bh 0.7ch 0.7dh 0.7eh 0.7fh 0.7eh.0 0.7fh.3 0.7fh.2 0.7fh.1 0.7fh.0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12 of the address register bits 11 to 8 of the address register bits 7 to 4 of the address register bits 3 to 0 of the address register window register bank register index register high memory pointer high memory pointer enable flag index register middle memory pointer low index register low general register pointer high general register pointer low program status word bcd flag compare flag carry flag zero flag index enable flag read/ write description value ar3 ar2 ar1 ar0 wr bank ixh mph mpe ixm mpl ixl rph rpl psw bcd cmp cy z ixe attribute symbol 22.3 vram bank register vrambank mem 2.73h r/w vram bank register read/ write description symbol attribute value
325 m pd17068 22.4 port register symbol attribute value read/ description write p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0d3 flg 0.73h.3 r bit 3 of port 0d p0d2 flg 0.73h.2 r bit 2 of port 0d p0d1 flg 0.73h.1 r bit 1 of port 0d p0d0 flg 0.73h.0 r bit 0 of port 0d p1a3 flg 1.70h.3 r/w bit 3 of port 1a p1a2 flg 1.70h.2 r/w bit 2 of port 1a p1a1 flg 1.70h.1 r/w bit 1 of port 1a p1a0 flg 1.70h.0 r/w bit 0 of port 1a p1b3 flg 1.71h.3 r/w bit 3 of port 1b p1b2 flg 1.71h.2 r/w bit 2 of port 1b p1b1 flg 1.71h.1 r/w bit 1 of port 1b p1b0 flg 1.71h.0 r/w bit 0 of port 1b p1c3 flg 1.72h.3 r/w bit 3 of port 1c p1c2 flg 1.72h.2 r/w bit 2 of port 1c p1c1 flg 1.72h.1 r/w bit 1 of port 1c p1c0 flg 1.72h.0 r/w bit 0 of port 1c p1d3 flg 1.73h.3 r/w bit 3 of port 1d p1d2 flg 1.73h.2 r/w bit 2 of port 1d p1d1 flg 1.73h.1 r/w bit 1 of port 1d p1d0 flg 1.73h.0 r/w bit 0 of port 1d p2a0 flg 2.70h.0 r/w bit 0 of port 2a
326 m pd17068 symbol attribute value read/ description write p2b3 flg 2.71h.3 r/w bit 3 of port 2b p2b2 flg 2.71h.2 r/w bit 2 of port 2b p2b1 flg 2.71h.1 r/w bit 1 of port 2b p2b0 flg 2.71h.0 r/w bit 0 of port 2b p2c3 flg 2.72h.3 r/w bit 3 of port 2c p2c2 flg 2.72h.2 r/w bit 2 of port 2c p2c1 flg 2.72h.1 r/w bit 1 of port 2c p2c0 flg 2.72h.0 r/w bit 0 of port 2c p2d2 flg 2.6fh.2 r/w bit 2 of port 2d p2d1 flg 2.6fh.1 r/w bit 1 of port 2d p2d0 flg 2.6fh.0 r/w bit 0 of port 2d
327 m pd17068 22.5 register files symbol attribute value read/ description write sp mem 0.81h r/w stack pointer ceedet flg 0.82h.0 r ce pin edge detection flag pwm8sel flg 0.83h.0 r/w pwm 8 /p2a 0 pin selection flag pwm7sel flg 0.84h.3 r/w pwm 7 /p2b 3 pin selection flag pwm6sel flg 0.84h.2 r/w pwm 6 /p2b 2 pin selection flag pwm5sel flg 0.84h.1 r/w pwm 5 /p2b 1 pin selection flag pwm4sel flg 0.84h.0 r/w pwm 4 /p2b 0 pin selection flag pwm3sel flg 0.85h.3 r/w pwm 3 /p2c 3 pin selection flag pwm2sel flg 0.85h.2 r/w pwm 2 /p2c 2 pin selection flag pwm1sel flg 0.85h.1 r/w pwm 1 /p2c 1 pin selection flag pwm0sel flg 0.85h.0 r/w pwm 0 /p2c 0 pin selection flag wtmhld flg 0.86h.3 r/w watch timer hold flag ckosel flg 0.86h.1 r/w p1b 1 /ckout pin selection flag xtsel flg 0.86h.0 r/w function selection flag of p0d 1 and p0d 0 pins ce flg 0.87h.0 r ce pin status flag sio0ch flg 0.88h.3 r/w sio0 channel selection flag sb flg 0.88h.2 r/w sio0 mode selection flag sio0ms flg 0.88h.1 r/w sio0 clock mode selection flag sio0tx flg 0.88h.0 r/w sio0 tx/rx selection flag tm0ck flg 0.89h.0 r/w timer 0 clock selection flag btm2exck flg 0.8ah.3 r/w bit 3 of basic timer 2 clock selection flag btm2zx flg 0.8ah.2 r/w bit 2 of basic timer 2 clock selection flag btm2ck1 flg 0.8ah.1 r/w bit 1 of basic timer 2 clock selection flag btm2ck0 flg 0.8ah.0 r/w bit 0 of basic timer 2 clock selection flag btm1exck flg 0.8bh.3 r/w bit 3 of basic timer 1 clock selection flag btm1zx flg 0.8bh.2 r/w bit 2 of basic timer 1 clock selection flag btm1ck1 flg 0.8bh.1 r/w bit 1 of basic timer 1 clock selection flag btm1ck0 flg 0.8bh.0 r/w bit 0 of basic timer 1 clock selection flag btm0ck1 flg 0.8ch.1 r/w bit 1 of basic timer 0 clock selection flag btm0ck0 flg 0.8ch.0 r/w bit 0 of basic timer 0 clock selection flag tm0rpt flg 0.8dh.2 r/w timer 0 mode (repeat) selection flag tm0res flg 0.8dh.1 w timer 0 reset flag tm0en flg 0.8dh.0 r/w timer 0 start/stop flag tm0ovf flg 0.8eh.0 r timer 0 overflow detection flag
328 m pd17068 symbol attribute value read/ description write igrp1sl flg 0.8fh.1 r/w interrupt request group 1 selection flag igrp0sl flg 0.8fh.0 r/w interrupt request group 0 selection flag hscgt1 flg 0.91h.1 r/w bit 1 of h sync -counter gate-mode selection flag hscgt0 flg 0.91h.0 r/w bit 0 of h sync -counter gate-mode selection flag hscgostt flg 0.92h.3 r h sync -counter gate open status flag pllrfck3 flg 0.93h.3 r/w bit 3 of pll reference clock selection flag pllrfck2 flg 0.93h.2 r/w bit 2 of pll reference clock selection flag pllrfck1 flg 0.93h.1 r/w bit 1 of pll reference clock selection flag pllrfck0 flg 0.93h.0 r/w bit 0 of pll reference clock selection flag wtmres3 flg 0.94h.3 r/w watch timer (day setting register) reset flag wtmres2 flg 0.94h.2 r/w watch timer (second/minute/hour setting register) reset flag wtmres1 flg 0.94h.1 r/w watch timer (basic clock) reset flag wtmres0 flg 0.94h.0 r/w watch timer (all) reset flag intncmd2 flg 0.95h.2 r/w bit 2 of int nc pulse width selection flag intncmd1 flg 0.95h.1 r/w bit 1 of int nc pulse width selection flag intncmd0 flg 0.95h.0 r/w bit 0 of int nc pulse width selection flag btm1cy flg 0.96h.0 r basic timer 1 carry flag btm0cy flg 0.97h.0 r basic timer 0 carry flag sback flg 0.98h.3 r/w sio0 acknowledge flag sio0nwt flg 0.98h.2 r/w sio0 not-wait flag sio0wrq1 flg 0.98h.1 r/w bit 1 of sio0 wait timing setting flag sio0wrq0 flg 0.98h.0 r/w bit 0 of sio0 wait timing setting flag sio0wstt flg 0.99h.0 r judge flag of sio0 wait status tm1ck1 flg 0.9ah.1 r/w bit 1 of timer 1 clock selection flag tm1ck0 flg 0.9ah.0 r/w bit 0 of timer 1 clock selection flag tm1res flg 0.9bh.1 r/w timer 1 reset flag tm1en flg 0.9bh.0 r/w timer 1 enable flag sio1ts flg 0.9ch.3 r/w sio1 start flag sio1hiz flg 0.9ch.2 r/w p2d 1 /so 1 pin selection flag sio1ck1 flg 0.9ch.1 r/w bit 1 of sio1 clock selection flag sio1ck0 flg 0.9ch.0 r/w bit 0 of sio1 clock selection flag wtm8hz flg 0.9dh.0 r watch timer 8 hz carry detection flag wtm128hz flg 0.9eh.0 r watch timer 128 hz carry detection flag
329 m pd17068 symbol attribute value read/ description write ieggrp1 flg 0.9fh.2 r/w interrupt group 1 edge detection selection flag ieg0 flg 0.9fh.1 r/w int 0 pin interrupt edge detection selection flag iegnc flg 0.9fh.0 r/w int nc pin interrupt edge detection selection flag rlsen flg 0.0a0h.0 r/w clock stop release setting flag with p1b 2 pin adcch2 flg 0.0a1h.2 r/w bit 2 of a/d converter channel selection flag adcch1 flg 0.0a1h.1 r/w bit 1 of a/d converter channel selection flag adcch0 flg 0.0a1h.0 r/w bit 0 of a/d converter channel selection flag pllul flg 0.0a2h.0 r pll unlock flip-flop flag adcen flg 0.0a4h.3 r/w a/d converter enable flag adccmp flg 0.0a4h.0 r/w a/d converter comparator output p2dbio2 flg 0.0a6h.2 r/w i/o selection flag of p2d 2 pin p2dbio1 flg 0.0a6h.1 r/w i/o selection flag of p2d 1 pin p2dbio0 flg 0.0a6h.0 r/w i/o selection flag of p2d 0 pin p1cgio flg 0.0a7h.0 r/w p1c group i/o selection flag sio0sf8 flg 0.0a8h.3 r sio0 shift 8 clock flag sio0sf9 flg 0.0a8h.2 r sio0 shift 9 clock flag sbstt flg 0.0a8h.1 r sio0 start condition detection flag sbbsy flg 0.0a8h.0 r sio0 busy condition detection flag irqgrp0 flg 0.0a9h.0 r/w interrupt group 0 (tm0ovf signal) interrupt request flag irqsio1 flg 0.0aah.0 r/w sio1 interrupt request flag irqsio0 flg 0.0abh.0 r/w sio0 interrupt request flag intgrp1 flg 0.0ach.3 r interrupt group 1 (h sync or v sync signal) interrupt status flag irqgrp1 flg 0.0ach.0 r/w interrupt group 1 (h sync or v sync signal) interrupt request flag ipgrp0 flg 0.0adh.1 r/w interrupt group 0 (tm0ovf signal) interrupt enable flag ipsio1 flg 0.0adh.0 r/w sio1 interrupt enable flag ipsio0 flg 0.0aeh.3 r/w sio0 interrupt enable flag ipgrp1 flg 0.0aeh.2 r/w interrupt group 1 (h sync or v sync signal) interrupt enable flag ipidcvp flg 0.0aeh.1 r/w idc vram pointer interrupt enable flag ipbtm2 flg 0.0aeh.0 r/w basic timer 2 interrupt enable flag iptm1 flg 0.0afh.3 r/w timer 1 interrupt enable flag iptm0 flg 0.0afh.2 r/w timer 0 interrupt enable flag ip0 flg 0.0afh.1 r/w int 0 pin interrupt enable flag ipnc flg 0.0afh.0 r/w int nc pin interrupt enable flag
330 m pd17068 symbol attribute value read/ description write idcbken flg 0.0b0h.3 r/w idc background color specification enable flag idcbkr flg 0.0b0h.2 r/w bit 2 of idc background color specification flag idcbkg flg 0.0b0h.1 r/w bit 1 of idc background color specification flag idcbkb flg 0.0b0h.0 r/w bit 0 of idc background color specification flag idcen flg 0.0b1h.0 r/w idc enable flag plulsen1 flg 0.0b2h.1 r/w bit 1 of pll unlock flip-flop sensibility selection flag plulsen0 flg 0.0b2h.0 r/w bit 0 of pll unlock flip-flop sensibility selection flag vramsel flg 0.0b3h.3 r/w vram selection flag idcisel flg 0.0b3h.2 r/w i pin selection flag idcd14sl flg 0.0b3h.1 r/w character dot (vertical) selection flag idccpch flg 0.0b3h.0 r/w selection flag for space between displayed characters p1b2edet flg 0.0b4h.0 r p1b 2 pin edge detection flag p1bbio3 flg 0.0b5h.3 r/w i/o selection flag of p1b 3 pin p1bbio2 flg 0.0b5h.2 r/w i/o selection flag of p1b 2 pin p1bbio1 flg 0.0b5h.1 r/w i/o selection flag of p1b 1 pin p1bbio0 flg 0.0b5h.0 r/w i/o selection flag of p1b 0 pin p0bbio3 flg 0.0b6h.3 r/w i/o selection flag of p0b 3 pin p0bbio2 flg 0.0b6h.2 r/w i/o selection flag of p0b 2 pin p0bbio1 flg 0.0b6h.1 r/w i/o selection flag of p0b 1 pin p0bbio0 flg 0.0b6h.0 r/w i/o selection flag of p0b 0 pin p0abio3 flg 0.0b7h.3 r/w i/o selection flag of p0a 3 pin p0abio2 flg 0.0b7h.2 r/w i/o selection flag of p0a 2 pin p0abio1 flg 0.0b7h.1 r/w i/o selection flag of p0a 1 pin p0abio0 flg 0.0b7h.0 r/w i/o selection flag of p0a 0 pin sio0imd1 flg 0.0b8h.1 r/w bit 1 of sio0 interrupt source register sio0imd0 flg 0.0b8h.0 r/w bit 0 of sio0 interrupt source register sio0ck1 flg 0.0b9h.1 r/w bit 1 of sio0 shift clock frequency selection flag sio0ck0 flg 0.0b9h.0 r/w bit 0 of sio0 shift clock frequency selection flag irqidcvp flg 0.0bah.0 r/w idc vram pointer interrupt request flag irqbtm2 flg 0.0bbh.0 r/w basic timer 2 interrupt request flag irqtm1 flg 0.0bch.0 r/w timer 1 interrupt request flag irqtm0 flg 0.0bdh.0 r/w timer 0 interrupt request flag int0 flg 0.0beh.3 r int 0 pin interrupt status flag irq0 flg 0.0beh.0 r/w int 0 pin interrupt request flag intnc flg 0.0bfh.3 r int nc pin interrupt status flag irqnc flg 0.0bfh.0 r/w int nc pin interrupt request flag
331 m pd17068 22.6 peripheral hardware register 22.7 others symbol attribute value read/ description write idcorg dat 01h r/w idc start position setting register adcr dat 02h r/w a/d-converter reference-voltage (v ref ) setting register sio0sfr dat 03h r/w sio0 shift register hsc dat 04h r h sync counter tm1m dat 05h r/w timer 1 modulo register tm1c dat 06h r timer 1 counter sio1sfr dat 07h r/w sio1 shift register pwmr0 dat 0ch w pwm data register 0 pwmr1 dat 0dh w pwm data register 1 pwmr2 dat 0eh w pwm data register 2 pwmr3 dat 0fh w pwm data register 3 pwmr4 dat 10h w pwm data register 4 pwmr5 dat 11h w pwm data register 5 pwmr6 dat 12h w pwm data register 6 pwmr7 dat 13h w pwm data register 7 pwmr8 dat 14h w pwm data register 8 wtmsec dat 1ah r/w register setting seconds of watch timer wtmmin dat 1bh r/w register setting minutes of watch timer wtmhr dat 1ch r/w register setting hours of watch timer wtmday dat 1dh r/w register setting days of watch timer ar dat 40h r/w address register for get/put/push/call/br/movt/movth/movtl instructions pllr dat 41h r/w pll data register idcvp dat 42h r idc vram pointer idcvpr dat 43h r/w idc vram pointer reference data register tm0m dat 46h r/w timer 0 modulo register tm0c dat 47h r timer 0 counter symbol attribute value description dbf dat 0fh fixed operand value for a put/get/movt instruction ix dat 01h fixed operand value for an inc instruction
332 m pd17068 23. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rated value unit supply voltage v dd C0.3 to +6.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o except p1a, p2b, and p2c C0.3 to v dd + 0.3 v output high current i oh one pin C12 ma all pins C20 ma output low current i ol1 one pin (except p1a) 12 ma all pins (except p1a) 20 ma output low current i ol2 one pin (p1a only) 17 ma all pins (p1a only) 60 ma output withstand voltage v bds p1a, p2a, p2b, p2c 13 v operating temperature t opt C40 to +85 c storage temperature t stg C55 to +125 c caution absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. be sure to use the product within the rated values. recommended operation range (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 4.5 5.0 5.5 v v dd2 when only the cpu is operating 3.5 5.0 5.5 v v dd3 when only the watch timer is operating (cpu is stopped) 2.2 5.0 5.5 v data hold voltage v ddr when clock is stopped (t a = 25 c) 2.2 5.5 v output withstand voltage v bds p1a, p2a, p2b, p2c 12.5 v supply voltage rise time t rise v dd = 0 ? 4.5 v 500 ms input amplitude v in vco 0.7 v dd v p-p
333 m pd17068 dc characteristics (t a = C40 to +85 c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit supply current i dd1 when all functions are operating, 20 23 ma v dd = 5 v, t a = 25 c, f in = 20 mhz, v in = 0.7 v p-p , when idc is operating, osc in = 10 mhz, when a sine signal is input to the x in pin, (f in = 8 mhz, v in = v dd ) i dd2 when the cpu and pll are operating, 9.0 12 ma v dd = 5 v, t a = 25 c, f in = 20 mhz v in = 0.7 v p-p , when a sine signal is input to the x in pin, (f in = 8 mhz, v in = v dd ) i dd3 when only the cpu is operating, 7.5 9 ma v dd = 5 v, t a = 25 c, when a sine signal is input to the x in pin, (f in = 8 mhz, v in = v dd ) i dd4 when the halt instruction is executed, 2.5 3 ma v dd = 5 v, t a = 25 c, when a sine signal is input to the x in pin, (f in = 8 mhz, v in = v dd ) data hold current i ddr1 when the main clock is stopped and the watch 4 15 m a timer is operating v dd = 5 v, t a = 25 c i ddr2 when the main clock and watch timer are stopped 3 15 m a v dd = 2.5 v, t a = 25 c input high voltage v ih1 p0a, p0b, p1b, p1c, p2d 0.7v dd v v ih2 ce, int 0 , int nc , v sync , h sync 0.8v dd v v ih3 p0d 0.7v dd v input low voltage v il1 p0a, p0b, p0d, p1b, p1c, p2d 0.2v dd v v il2 ce, int 0 , int nc , v sync , h sync 0.2v dd v output high current i oh p0a 2 , p0a 3 , p0b, p0c, p1b, p1c, blank, red, C1 C5 ma green, blue, p1d, p2d, eo v oh = v dd C 1 v output low current i ol1 p0a, p0b, p0c, p1b, p1c, blank, red, green, 1 8.5 ma blue, p1d, p2a, p2b, p2c, p2d, eo, pwm v ol = 1 v i ol2 p1a v ol = 1 v 15 33 ma input high current i ih vco v ih = v dd 0.1 0.85 1.3 ma output leakage high current i loh p1a, p2a, p2b, p2c v o = 12.5 v 0.5 m a output off leakage current i l eo v o = v dd or 0 v 10 C3 1 m a built-in pull-down r pd1 p0d (key) v ih = v dd 19 36 69 k w r pd2 p0d (key) v ih = v dd = 5 v 23 36 56 k w r pd3 p0d (key) v ih = v dd = 5 v, t a = 25 c 293641k w resistor
334 m pd17068 ac characteristics (t a = C40 to +85 c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit input frequency 1 f vco when a sine signal is input to the vco pin 0.7 20 mhz v in = 0.7v p-p input frequency 2 f tmr tmin (p1b 3 ) 50 % duty cycle 45 65 hz input frequency 3 f hs hscnt (p0b 3 ) 10 20 khz a/d converter characteristics (t a = C10 to +50 c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit a/d conversion adc 0 to adc 7 1 1.5 lsb absolute accuracy a/d conversion adc 0 to adc 7 6 bit resolution a/d input impedance adc 0 to adc 7 1m w
335 m pd17068 24. package drawings 23.2?.4 20.0?.2 80 81 51 50 1 100 30 31 14.0?.2 17.2?.4 3.0 max. 0.1?.1 55 0.30?.10 0.6 0.15 0.65 m 1.6?.2 0.8?.2 0.15 -0.05 +0.10 0.12 2.7 0.8 s100gf-65-3ba-1
336 m pd17068 25. recommended soldering conditions the conditions listed below shall be met when soldering the m pd17068. for details of the recommended soldering conditions, refer to our document smd surface mount technology manual (iei-1207) . please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 25-1 soldering conditions for surface-mount devices m pd17068gf- -3ba: 100-pin plastic qfp (14 20 mm) m pd17068gf-e -3ba: 100-pin plastic qfp (14 20 mm) note exposure limit before soldering after dry-pack package is opened. storage conditions: temperature of 25 ?c and maximum relative humidity at 65% or less caution do not apply more than a single process at once, except for partial heating method. symbol ir35-207-2 vp15-207-2 ws60-207-1 C soldering process infrared ray reflow vps wave soldering partial heating method soldering conditions peak packages surface temperature: 235 ?c reflow time: 30 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 2 exposure limit note : 7 days (20 hours of pre-baking is required at 125 ?c afterward.) (1) do not start reflow-soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering. (2) do not use water for flux cleaning before a second reflow soldering. peak packages surface temperature: 215 ?c reflow time: 40 seconds or less (at 200 ?c or more) maximum allowable number of reflow processes: 2 exposure limit note : 7 days (20 hours of pre-baking is required at 125 ?c afterward.) (1) do not start reflow-soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering. (2) do not use water for flux cleaning before a second reflow soldering. solder temperature: 260 ?c or less flow time: 10 seconds or less number of flow process: 1 preheating temperature: 120 ?c max. (measured on the package surface) exposure limit note : 7 days (20 hours of pre-baking is required at 125 c afterward.) terminal temperature: 300 ?c or less heat time: 3 seconds or less (for each side of device)
337 m pd17068 c2 c1 x out , xt out x in , xt in 8 mhz crystal pd17068 m appendix a. notes on connecting a crystal when connecting the crystal, run wires in the portion surrounded by dotted lines in fig. a-1 according to the following rules to avoid effects such as stray capacitance: ? minimize the wiring. ? never cause the wires to cross other signal lines or run near a line carrying a large varying current. ? cause the grounding point of the capacitor of the oscillator circuit to have the same potential as ground. never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator. note the following (1) to (3) when capacitors are connected or the oscillation frequency is adjusted. (1) when c1 and c2 are too large, the oscillation activation characteristics deteriorate and the supply current increases. (2) the trimmer capacitor for adjusting the oscillation frequency is usually connected to the x in (or xt in ) pin. however, this connection may cause deterioration of oscillation stability, depending on the crystal used. (in this case, connect the trimmer capacitor to the x out (or xt out ) pin.) to evaluate the oscillation, use the crystal to be actually used. (3) adjust the oscillation frequency while measuring the vco oscillation frequency. if the probe is connected to pin x out , xt out , x in , or xt in , the oscillation frequency cannot be correctly adjusted because of the probe capacitance. fig. a-1 crystal connection
338 m pd17068 name description appendix b. development tools the following support tools are available for developing programs for the m pd17068. hardware the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators applicable to the 17k series. the ie-17k and ie-17k-et are connected to the pc-9800 series (host machine) or ibm pc/at tm through the rs-232-c interface. the emu-17k is inserted into the extension slot of the pc-9800 series (host machine). use the system evaluation board (se board) corresponding to each product together with one of these in-circuit emulators. simplehost tm , a man machine interface, implements an advanced debug environment. the emu-17k also enables user to check the contents of the data memory in real time. the se-17008 is an se board for the m pd17068, m pd17p068, and m pd17008. it is used solely for evaluating the system. it is also used for debugging in combination with the in-circuit emulator. the ep-17068gf is an emulation probe for the m pd17068 and m pd17p068. the ev-9200gf-100 is a conversion socket for the 100-pin plastic qfp (14 20 mm). it is used to connect the ep-17068gf to the target system. the af-9703, af-9704, af-9705, and af-9706 are prom writers for the m pd17p068. use one of these prom writers with the program adapter, af-9808l, to program the m pd17p068. the af-9808l is a socket unit for the m pd17p068. it is used with the af-9703, af-9704, af-9705, or af-9706. notes 1. low-end model, operating on an external power supply 2. the emu-17k is a product of ic co., ltd. contact ic co., ltd. (tokyo, 03-3447-3793) for details. 3. the ep-17068gf is supplied together with one ev-9200gf-100. a set of five ev-9200gf-100s is also available. 4. the af-9703, af-9704, af-9705, af-9706, and af-9808l are products of ando electric co., ltd. contact ando electric co., ltd. (tokyo, 03-3733-1151) for details. in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17008) emulation probe (ep-17068gf) conversion socket (ev-9200gf-100 note 3 ) prom programmer af-9703 note 4 af-9704 note 4 af-9705 note 4 af-9706 note 4 programmer adapter (af-9808l note 4 )
339 m pd17068 17k series assembler (as17k) device file (as17068) support software (simplehost) m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17068 m s5a13as17068 m s7b10as17068 m s7b13as17068 m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k as17k is an assembler applicable to the 17k series. in developing m pd17068 programs, as17k is used in combination with a device file (as17068). as17068 is a device file for the m pd17068 and m pd17p068 . it is used together with the assembler (as17k), which is applicable to the 17k series. simplehost, running on the windows tm , provides man- machine-interface in devel- oping programs by using a personal computer and the in-circuit emulator. os part number description distribution media host machine software 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at name ms-dos pc dos windows ms-dos tm pc dos tm ms-dos pc dos remark the following table lists the versions of the operating systems described in the above table. os versions ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note ms-dos versions 5.00 and 5.00a and pc dos ver. 5.0 are provided with a task swap function. this function, however, cannot be used in these software packages.
m pd17068 cautions on cmos devices # countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. $ cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate-level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. % statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first. caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
m pd17068 simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 [memo]

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